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SN74LVT125-EP PDF预览

SN74LVT125-EP

更新时间： 2024-01-14 14:05:37
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德州仪器 - TI 输出元件
页数 文件大小 规格书
11页 485K
描述
3.3-V ABT QUADRUPLE BUS BUFFER WITH 3-STATE OUTPUTS

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SN74LVT125-EP 数据手册

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SN74LVT125-EP  
3.3-V ABT QUADRUPLE BUS BUFFER  
WITH 3-STATE OUTPUTS  
www.ti.com  
SCBS796A–JANUARY 2004–REVISED JUNE 2005  
FEATURES  
•
•
•
•
Supports Unregulated Battery Operation  
Down to 2.7 V  
•
Controlled Baseline  
Typical VOLP (Output Ground Bounce) < 0.8 V  
at VCC = 3.3 V, TA = 25°C  
– One Assembly/Test Site, One Fabrication  
Site  
Ioff Supports Partial-Power-Down Mode  
Operation  
•
•
Extended Temperature Performance of  
–40°C to 125°C  
Bus-Hold Data Inputs Eliminate the Need for  
External Pullup Resistors  
Enhanced Diminishing Manufacturing  
Sources (DMS) Support  
•
•
•
Enhanced Product-Change Notification  
Qualification Pedigree(1)  
D OR PW PACKAGE  
(TOP VIEW)  
ESD Protection Exceeds 2000 V Per  
MIL-STD-883, Method 3015; Exceeds 200 V  
Using Machine Model (C = 200 pF, R = 0)  
V
CC  
14  
1
2
3
4
5
6
7
1OE  
1A  
13 4OE  
12 4A  
1Y  
•
Supports Mixed-Mode Signal Operation (5-V  
Input and Output Voltages With 3.3-V VCC  
11  
10  
9
4Y  
2OE  
2A  
2Y  
)
3OE  
3A  
(1)  
Component qualification in accordance with JEDEC and  
industry standards to ensure reliable operation over an  
8
3Y  
GND  
extended temperature range. This includes, but is not limited  
to, Highly Accelerated Stress Test (HAST) or biased 85/85,  
temperature cycle, autoclave or unbiased HAST,  
electromigration, bond intermetallic life, and mold compound  
life. Such qualification testing should not be viewed as  
justifying use of this component beyond specified  
performance and environmental limits.  
DESCRIPTION/ORDERING INFORMATION  
This bus buffer is designed specifically for low-voltage (3.3-V) VCC operation, but with the capability to provide a  
TTL interface to a 5-V system environment.  
The SN74LVT125 features independent line drivers with 3-state outputs. Each output is in the high-impedance  
state when the associated output-enable (OE) input is high.  
Active bus-hold circuitry holds unused or undriven inputs at a valid logic state. Use of pullup or pulldown resistors  
with the bus-hold circuitry is not recommended.  
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs,  
preventing damaging current backflow through the device when it is powered down.  
To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup  
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.  
ORDERING INFORMATION  
TA  
PACKAGE(1)  
Tape and reel  
Tape and reel  
ORDERABLE PART NUMBER  
SN74LVT125QDREP  
TOP-SIDE MARKING  
LVT125E  
SOIC – D  
–40°C to 125°C  
TSSOP – PW  
SN74LVT125QPWREP  
LVT125E  
(1) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at  
www.ti.com/sc/package.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas  
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
PRODUCTION DATA information is current as of publication date.  
Copyright © 2004–2005, Texas Instruments Incorporated  
Products conform to specifications per the terms of the Texas  
Instruments standard warranty. Production processing does not  
necessarily include testing of all parameters.  
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