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SN74LVT125-Q1 PDF预览

SN74LVT125-Q1

更新时间： 2024-02-15 03:34:15
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德州仪器 - TI 输出元件
页数 文件大小 规格书
10页 228K
描述
3.3-V ABT QUADRUPLE BUS BUFFER WITH 3-STATE OUTPUTS

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SN74LVT125-Q1 数据手册

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SN74LVT125-Q1  
www.ti.com....................................................................................................................................................... SCBS763B–AUGUST 2003–REVISED APRIL 2008  
3.3-V ABT QUADRUPLE BUS BUFFER  
WITH 3-STATE OUTPUTS  
1
FEATURES  
•
Qualified for Automotive Applications  
D OR PW PACKAGE  
(TOP VIEW)  
•
ESD Protection Exceeds 2000 V Per  
MIL-STD-883, Method 3015; Exceeds 200 V  
Using Machine Model (C = 200 pF, R = 0)  
1
2
3
4
5
6
7
14  
13  
12  
11  
10  
9
1OE  
1A  
VCC  
4OE  
4A  
4Y  
3OE  
3A  
•
•
•
•
•
Supports Mixed-Mode Signal Operation (5-V  
1Y  
2OE  
2A  
2Y  
GND  
Input and Output Voltages With 3.3-V VCC  
)
Supports Unregulated Battery Operation Down  
to 2.7 V  
Typical VOLP (Output Ground Bounce)  
<0.8 V at VCC = 3.3 V, TA = 25°C  
8
3Y  
Ioff Supports Partial-Power-Down Mode  
Operation  
Bus-Hold Data Inputs Eliminate the Need for  
External Pullup Resistors  
DESCRIPTION/ORDERING INFORMATION  
This bus buffer is designed specifically for low-voltage (3.3-V) VCC operation, but with the capability to provide a  
TTL interface to a 5-V system environment.  
The SN74LVT125-Q1 features independent line drivers with 3-state outputs. Each output is in the  
high-impedance state when the associated output-enable (OE) input is high.  
Active bus-hold circuitry holds unused or undriven inputs at a valid logic state. Use of pullup or pulldown resistors  
with the bus-hold circuitry is not recommended.  
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs,  
preventing damaging current backflow through the device when it is powered down.  
To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup  
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.  
ORDERING INFORMATION(1)  
TA  
PACKAGE(2)  
Tape and reel  
Tape and reel  
ORDERABLE PART NUMBER  
SN74LVT125QDRQ1  
TOP-SIDE MARKING  
LVT125Q  
LVT125Q  
SOIC – D  
–40°C to 125°C  
TSSOP – PW  
SN74LVT125QPWRQ1  
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI  
web site at www.ti.com.  
(2) Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.  
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
PRODUCTION DATA information is current as of publication date.  
Copyright © 2003–2008, Texas Instruments Incorporated  
Products conform to specifications per the terms of the Texas  
Instruments standard warranty. Production processing does not  
necessarily include testing of all parameters.  
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