SN74LVC1G74DCTR-P

更新时间： 2024-11-21 13:13:51

品牌	Logo	应用领域
德州仪器 - TI		触发器
页数	文件大小	规格书
19页	720K
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SN74LVC1G74

www.ti.com

SCES794B –SEPTEMBER 2009–REVISED FEBRUARY 2012

SINGLE POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP

WITH CLEAR AND PRESET

Check for Samples: SN74LVC1G74

FEATURES

•

Available in the Texas Instruments NanoFree™

Package

•

I_offSupports Live Insertion, Partial Power

Down Mode, and Back Drive Protection

•

Supports 5-V V_CCOperation

Inputs Accept Voltages to 5.5 V

Max t_pdof 5.9 ns at 3.3 V

Latch-Up Performance Exceeds 100 mA Per

JESD 78, Class II

ESD Protection Exceeds JESD 22

–

2000-V Human-Body Model (A114-A)

200-V Machine Model (A115-A)

Low Power Consumption, 10-μA Max I_CC

±24-mA Output Drive at 3.3 V

1000-V Charged-Device Model (C101)

Typical V_OLP(Output Ground Bounce)

<0.8 V at V_CC= 3.3 V, T_A= 25°C

•

Typical V_OHV(Output V_OHUndershoot)

>2 V at V_CC= 3.3 V, T_A= 25°C

DCT PACKAGE

(TOP VIEW)

DCU PACKAGE

(TOP VIEW)

YZP PACKAGE

(TOP VIEW)

1 8

2 7

3 6

4 5

V_CC

PRE

CLR

V_CC

CLK

GND

V_CC

CLK

PRE

CLR

PRE

CLR

GND

See mechanical drawings for dimensions.

DESCRIPTION/ORDERING INFORMATION

This single positive-edge-triggered D-type flip-flop is designed for 1.65-V to 5.5-V V_CCoperation.

NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the die as the

package.

A low level at the preset (PRE) or clear (CLR) input sets or resets the outputs, regardless of the levels of the

other inputs. When PRE and CLR are inactive (high), data at the data (D) input meeting the setup time

requirements is transferred to the outputs on the positive-going edge of the clock pulse. Clock triggering occurs

at a voltage level and is not related directly to the rise time of the clock pulse. Following the hold-time interval,

data at the D input can be changed without affecting the levels at the outputs.

This device is fully specified for partial-power-down applications using I_off. The I_offcircuitry disables the outputs,

preventing damaging current backflow through the device when it is powered down.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

NanoFree is a trademark of Texas Instruments.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

12 3 4 5 6 7...19

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与SN74LVC1G74DCTR-P相关器件

型号	品牌	获取价格	描述	数据表
SN74LVC1G74DCU	TI	获取价格	SINGLE POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH CLEAR AND PRESET
SN74LVC1G74DCU6	TI	获取价格	SINGLE POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH CLEAR AND PRESET
SN74LVC1G74DCUR	TI	获取价格	SINGLE POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH CLEAR AND PRESET
SN74LVC1G74DCURG4	TI	获取价格	SINGLE POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH CLEAR AND PRESET
SN74LVC1G74DCUR-P	TI	获取价格	LVC/LCX/Z SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO8, PLASTI
SN74LVC1G74DCUT	TI	获取价格	SINGLE POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH CLEAR AND PRESET
SN74LVC1G74DQER	TI	获取价格	Available in the Texas Instruments NanoFreeâ
SN74LVC1G74RSE2	TI	获取价格	具有清零和预置端的单路正边沿触发式 D 型触发器 \| RSE \| 8 \| -40 to 1
SN74LVC1G74RSER	TI	获取价格	具有清零和预置端的单路正边沿触发式 D 型触发器 \| RSE \| 8 \| -40 to 1
SN74LVC1G74YZPR	TI	获取价格	SINGLE POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH CLEAR AND PRESET

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