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SN74LVC1G74DCUR-P PDF预览

SN74LVC1G74DCUR-P

更新时间： 2024-11-04 21:09:47
品牌 Logo 应用领域
德州仪器 - TI 光电二极管输出元件逻辑集成电路触发器
页数 文件大小 规格书
17页 617K
描述
LVC/LCX/Z SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO8, PLASTIC, VSSOP-8

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SN74LVC1G74DCUR-P 技术参数

生命周期：Obsolete零件包装代码：SOIC
包装说明：VSSOP, TSSOP8,.12,20针数：8
Reach Compliance Code：unknownHTS代码：8542.39.00.01
风险等级：5.13系列：LVC/LCX/Z
JESD-30 代码：R-PDSO-G8长度：2.3 mm
逻辑集成电路类型：D FLIP-FLOP最大频率@ Nom-Sup：175000000 Hz
最大I（ol）：0.024 A位数：1
功能数量：1端子数量：8
最高工作温度：85 °C最低工作温度：-40 °C
输出极性：COMPLEMENTARY封装主体材料：PLASTIC/EPOXY
封装代码：VSSOP封装等效代码：TSSOP8,.12,20
封装形状：RECTANGULAR封装形式：SMALL OUTLINE, VERY THIN PROFILE, SHRINK PITCH
包装方法：TAPE AND REEL电源：3.3 V
Prop。Delay @ Nom-Sup：5.9 ns传播延迟（tpd）：14.4 ns
认证状态：Not Qualified座面最大高度：0.9 mm
子类别：FF/Latch最大供电电压 (Vsup)：5.5 V
最小供电电压 (Vsup)：1.65 V标称供电电压 (Vsup)：3.3 V
表面贴装：YES技术：CMOS
温度等级：INDUSTRIAL端子形式：GULL WING
端子节距：0.5 mm端子位置：DUAL
触发器类型：POSITIVE EDGE宽度：2 mm
最小 fmax：200 MHzBase Number Matches：1

SN74LVC1G74DCUR-P 数据手册

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SN74LVC1G74  
www.ti.com ............................................................................................................................................................................................. SCES794–OCTOBER 2009  
SINGLE POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP  
WITH CLEAR AND PRESET  
1
FEATURES  
2
•
Available in the Texas Instruments NanoFree™  
Package  
•
•
•
•
Typical VOHV (Output VOH Undershoot)  
>2 V at VCC = 3.3 V, TA = 25°C  
•
•
•
•
•
•
Supports 5-V VCC Operation  
Ioff Supports Partial-Power-Down Mode  
Operation  
Inputs Accept Voltages to 5.5 V  
Max tpd of 5.9 ns at 3.3 V  
Latch-Up Performance Exceeds 100 mA Per  
JESD 78, Class II  
Low Power Consumption, 10-µA Max ICC  
±24-mA Output Drive at 3.3 V  
ESD Protection Exceeds JESD 22  
–
–
2000-V Human-Body Model (A114-A)  
1000-V Charged-Device Model (C101)  
Typical VOLP (Output Ground Bounce)  
<0.8 V at VCC = 3.3 V, TA = 25°C  
DCT PACKAGE  
(TOP VIEW)  
DCU PACKAGE  
(TOP VIEW)  
YZP PACKAGE  
(TOP VIEW)  
A1  
B1  
C1  
D1  
A2  
B2  
C2  
D2  
1 8  
2 7  
3 6  
4 5  
VCC  
PRE  
CLR  
Q
VCC  
1
2
3
4
8
7
6
5
CLK  
CLK  
D
Q
GND  
VCC  
1
2
3
4
8
7
6
5
CLK  
D
PRE  
CLR  
Q
D
Q
PRE  
CLR  
Q
GND  
Q
GND  
See mechanical drawings for dimensions.  
DESCRIPTION/ORDERING INFORMATION  
This single positive-edge-triggered D-type flip-flop is designed for 1.65-V to 5.5-V VCC operation.  
NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the die as the  
package.  
A low level at the preset (PRE) or clear (CLR) input sets or resets the outputs, regardless of the levels of the  
other inputs. When PRE and CLR are inactive (high), data at the data (D) input meeting the setup time  
requirements is transferred to the outputs on the positive-going edge of the clock pulse. Clock triggering occurs  
at a voltage level and is not related directly to the rise time of the clock pulse. Following the hold-time interval,  
data at the D input can be changed without affecting the levels at the outputs.  
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs,  
preventing damaging current backflow through the device when it is powered down.  
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas  
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
2
NanoFree is a trademark of Texas Instruments.  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of the Texas  
Instruments standard warranty. Production processing does not  
necessarily include testing of all parameters.  
Copyright © 2009, Texas Instruments Incorporated  
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