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SN74LVC1G74RSE2

更新时间： 2023-06-19 15:25:31
品牌 Logo 应用领域
德州仪器 - TI 触发器锁存器
页数 文件大小 规格书
19页 720K
描述
具有清零和预置端的单路正边沿触发式 D 型触发器 | RSE | 8 | -40 to 125

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SN74LVC1G74RSE2 数据手册

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SN74LVC1G74  
www.ti.com  
SCES794B –SEPTEMBER 2009–REVISED FEBRUARY 2012  
SINGLE POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP  
WITH CLEAR AND PRESET  
Check for Samples: SN74LVC1G74  
1
FEATURES  
2
•
Available in the Texas Instruments NanoFree™  
Package  
•
•
•
Ioff Supports Live Insertion, Partial Power  
Down Mode, and Back Drive Protection  
•
•
•
•
•
•
Supports 5-V VCC Operation  
Inputs Accept Voltages to 5.5 V  
Max tpd of 5.9 ns at 3.3 V  
Latch-Up Performance Exceeds 100 mA Per  
JESD 78, Class II  
ESD Protection Exceeds JESD 22  
–
–
–
2000-V Human-Body Model (A114-A)  
200-V Machine Model (A115-A)  
Low Power Consumption, 10-μA Max ICC  
±24-mA Output Drive at 3.3 V  
1000-V Charged-Device Model (C101)  
Typical VOLP (Output Ground Bounce)  
<0.8 V at VCC = 3.3 V, TA = 25°C  
•
Typical VOHV (Output VOH Undershoot)  
>2 V at VCC = 3.3 V, TA = 25°C  
DCT PACKAGE  
(TOP VIEW)  
DCU PACKAGE  
(TOP VIEW)  
YZP PACKAGE  
(TOP VIEW)  
A1  
B1  
C1  
D1  
A2  
B2  
C2  
D2  
1 8  
2 7  
3 6  
4 5  
VCC  
PRE  
CLR  
Q
VCC  
1
2
3
4
8
7
6
5
CLK  
D
CLK  
D
Q
GND  
VCC  
1
2
3
4
8
7
6
5
CLK  
D
PRE  
CLR  
Q
PRE  
CLR  
Q
Q
GND  
Q
GND  
See mechanical drawings for dimensions.  
DESCRIPTION/ORDERING INFORMATION  
This single positive-edge-triggered D-type flip-flop is designed for 1.65-V to 5.5-V VCC operation.  
NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the die as the  
package.  
A low level at the preset (PRE) or clear (CLR) input sets or resets the outputs, regardless of the levels of the  
other inputs. When PRE and CLR are inactive (high), data at the data (D) input meeting the setup time  
requirements is transferred to the outputs on the positive-going edge of the clock pulse. Clock triggering occurs  
at a voltage level and is not related directly to the rise time of the clock pulse. Following the hold-time interval,  
data at the D input can be changed without affecting the levels at the outputs.  
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs,  
preventing damaging current backflow through the device when it is powered down.  
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas  
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
2
NanoFree is a trademark of Texas Instruments.  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of the Texas  
Instruments standard warranty. Production processing does not  
necessarily include testing of all parameters.  
Copyright © 2009–2012, Texas Instruments Incorporated  
 
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SN74LVC1G74RSE2 替代型号

型号 品牌 替代类型 描述 数据表
SN74LVC1G74RSER TI

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