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SN74LVC1G79DBV PDF预览

SN74LVC1G79DBV

更新时间： 2024-11-03 22:22:23
品牌 Logo 应用领域
德州仪器 - TI 触发器锁存器逻辑集成电路光电二极管
页数 文件大小 规格书
15页 356K
描述
SINGLE POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP

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中文翻译

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SN74LVC1G79DBV 技术参数

是否Rohs认证： 不符合生命周期：Obsolete
包装说明：TSOP, TSOP5/6,.11,37Reach Compliance Code：not_compliant
风险等级：5.89Is Samacsys：N
JESD-30 代码：R-PDSO-G5负载电容（CL）：50 pF
逻辑集成电路类型：D FLIP-FLOP最大I（ol）：0.024 A
功能数量：1端子数量：5
最高工作温度：85 °C最低工作温度：-40 °C
封装主体材料：PLASTIC/EPOXY封装代码：TSOP
封装等效代码：TSOP5/6,.11,37封装形状：RECTANGULAR
封装形式：SMALL OUTLINE, THIN PROFILE电源：3.3 V
认证状态：Not Qualified子类别：FF/Latches
标称供电电压 (Vsup)：3.3 V表面贴装：YES
技术：CMOS温度等级：INDUSTRIAL
端子形式：GULL WING端子节距：0.95 mm
端子位置：DUAL触发器类型：POSITIVE EDGE
Base Number Matches：1

SN74LVC1G79DBV 数据手册

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SCES220N − APRIL 1999 − REVISED SEPTEMBER 2003  
DBV OR DCK PACKAGE  
(TOP VIEW)  
D
Available in the Texas Instruments  
NanoStarand NanoFreePackages  
Supports 5-V V Operation  
D
D
D
D
D
D
D
D
CC  
1
2
3
5
4
D
CLK  
GND  
V
CC  
Inputs Accept Voltages to 5.5 V  
Max t of 4 ns at 3.3 V  
pd  
Low Power Consumption, 10-µA Max I  
Q
CC  
YEA, YEP, YZA, OR YZP PACKAGE  
(BOTTOM VIEW)  
24-mA Output Drive at 3.3 V  
I
Supports Partial-Power-Down Mode  
off  
Operation  
3 4  
2
GND  
CLK  
D
Q
Latch-Up Performance Exceeds 100 mA Per  
JESD 78, Class II  
1 5  
V
CC  
ESD Protection Exceeds JESD 22  
− 2000-V Human-Body Model (A114-A)  
− 200-V Machine Model (A115-A)  
− 1000-V Charged-Device Model (C101)  
description/ordering information  
This single positive-edge-triggered D-type flip-flop is designed for 1.65-V to 5.5-V V  
operation.  
CC  
When data at the data (D) input meets the setup time requirement, the data is transferred to the Q output on  
the positive-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not directly related  
to the rise time of the clock pulse. Following the hold-time interval, data at the D input can be changed without  
affecting the level at the output.  
NanoStarand NanoFreepackage technology is a major breakthrough in IC packaging concepts, using the  
die as the package.  
ORDERING INFORMATION  
ORDERABLE  
PART NUMBER  
TOP-SIDE  
MARKING  
†
T
A
PACKAGE  
‡
NanoStar− WCSP (DSBGA)  
0.17-mm Small Bump − YEA  
SN74LVC1G79YEAR  
SN74LVC1G79YZAR  
SN74LV1G79YEPR  
SN74LV1G79YZPR  
NanoFree− WCSP (DSBGA)  
0.17-mm Small Bump − YZA (Pb-free)  
Reel of 3000  
_ _ _CR_  
NanoStar− WCSP (DSBGA)  
0.23-mm Large Bump − YEP  
−40°C to 85°C  
NanoFree− WCSP (DSBGA)  
0.23-mm Large Bump − YZP (Pb-free)  
Reel of 3000  
Reel of 250  
Reel of 3000  
SN74LVC1G79DBVR  
SN74LVC1G79DBVT  
SN74LVC1G79DCKR  
SOT (SOT-23) − DBV  
SOT (SC-70) − DCK  
C79_  
CR_  
Reel of 250  
SN74LVC1G79DCKT  
†
‡
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at  
www.ti.com/sc/package.  
DBV/DCK: The actual top-side marking has one additional character that designates the assembly/test site.  
YEA/YZA, YEP/YZP: The actual top-side marking has three preceding characters to denote year, month, and sequence code,  
and one following character to designate the assembly/test site. Pin 1 identifier indicates solder-bump composition  
(1 = SnPb, • = Pb-free).  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
NanoStar and NanoFree are trademarks of Texas Instruments.  
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Copyright 2003, Texas Instruments Incorporated  
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ꢝ ꢡ ꢞ ꢝꢖ ꢗꢫ ꢙꢘ ꢜ ꢤꢤ ꢢꢜ ꢚ ꢜ ꢛ ꢡ ꢝ ꢡ ꢚ ꢞ ꢦ  
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1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567...15

中文翻译

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