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SN74LVC1G79-EP PDF预览

SN74LVC1G79-EP

更新时间： 2024-01-28 20:33:57
品牌 Logo 应用领域
德州仪器 - TI 触发器
页数 文件大小 规格书
11页 373K
描述
SINGLE POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP

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SN74LVC1G79-EP 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Active零件包装代码：BGA
包装说明：VFBGA, BGA5,2X3,20针数：5
Reach Compliance Code：compliantECCN代码：EAR99
HTS代码：8542.39.00.01Factory Lead Time：1 week
风险等级：1.35系列：LVC/LCX/Z
JESD-30 代码：R-XBGA-B5JESD-609代码：e1
长度：1.4 mm负载电容（CL）：50 pF
逻辑集成电路类型：D FLIP-FLOP最大频率@ Nom-Sup：160000000 Hz
最大I（ol）：0.032 A湿度敏感等级：1
位数：1功能数量：1
端子数量：5最高工作温度：85 °C
最低工作温度：-40 °C输出特性：3-STATE
输出极性：TRUE封装主体材料：UNSPECIFIED
封装代码：VFBGA封装等效代码：BGA5,2X3,20
封装形状：RECTANGULAR封装形式：GRID ARRAY, VERY THIN PROFILE, FINE PITCH
包装方法：TR峰值回流温度（摄氏度）：260
电源：3.3 V最大电源电流（ICC）：0.01 mA
Prop。Delay @ Nom-Sup：5 ns传播延迟（tpd）：20.5 ns
认证状态：Not Qualified座面最大高度：0.5 mm
子类别：FF/Latches最大供电电压 (Vsup)：5.5 V
最小供电电压 (Vsup)：1.65 V标称供电电压 (Vsup)：1.8 V
表面贴装：YES技术：CMOS
温度等级：INDUSTRIAL端子面层：Tin/Silver/Copper (Sn/Ag/Cu)
端子形式：BALL端子节距：0.5 mm
端子位置：BOTTOM处于峰值回流温度下的最长时间：NOT SPECIFIED
触发器类型：POSITIVE EDGE宽度：0.9 mm
最小 fmax：160 MHzBase Number Matches：1

SN74LVC1G79-EP 数据手册

 浏览型号SN74LVC1G79-EP的Datasheet PDF文件第2页浏览型号SN74LVC1G79-EP的Datasheet PDF文件第3页浏览型号SN74LVC1G79-EP的Datasheet PDF文件第4页浏览型号SN74LVC1G79-EP的Datasheet PDF文件第5页浏览型号SN74LVC1G79-EP的Datasheet PDF文件第6页浏览型号SN74LVC1G79-EP的Datasheet PDF文件第7页 
SN74LVC1G79-EP  
www.ti.com....................................................................................................................................................... SCES646A–AUGUST 2005–REVISED APRIL 2009  
SINGLE POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP  
1
FEATURES  
•
•
•
•
•
•
Supports 5-V VCC Operation  
Inputs Accept Voltages to 5.5 V  
Max tpd of 5 ns at 3.3 V  
SUPPORTS DEFENSE, AEROSPACE,  
AND MEDICAL APPLICATIONS  
•
•
•
•
Controlled Baseline  
One Assembly/Test Site  
One Fabrication Site  
Available in Military (–55°C/125°C)  
Temperature Range(1)  
Low Power Consumption, 10-µA Max ICC  
±24-mA Output Drive at 3.3 V  
Ioff Supports Partial-Power-Down Mode  
Operation  
•
•
•
Extended Product Life Cycle  
Extended Product-Change Notification  
Product Traceability  
•
•
Latch-Up Performance Exceeds 100 mA Per  
JESD 78, Class II  
ESD Protection Exceeds JESD 22  
DCK PACKAGE  
(TOP VIEW)  
–
–
–
2000-V Human-Body Model (A114-A)  
200-V Machine Model (A115-A)  
D
CLK  
GND  
VCC  
1
2
3
5
1000-V Charged-Device Model (C101)  
4
Q
See mechanical drawings for dimensions.  
(1) Additional temperature ranges are available - contact factory  
DESCRIPTION/ORDERING INFORMATION  
This single positive-edge-triggered D-type flip-flop is designed for 1.65-V to 5.5-V VCC operation.  
When data at the data (D) input meets the setup time requirement, the data is transferred to the Q output on the  
positive-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not directly related to the  
rise time of the clock pulse. Following the hold-time interval, data at the D input can be changed without affecting  
the level at the output.  
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs,  
preventing damaging current backflow through the device when it is powered down.  
ORDERING INFORMATION  
TA  
PACKAGE(1)  
ORDERABLE PART NUMBER  
TOP-SIDE MARKING(2)  
CR_  
–55°C to 115°C SOT (SC-70) – DCK  
Reel of 3000  
SN74LVC1G79WDCKREP  
(1) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at  
www.ti.com/sc/package.  
(2) DCK: The actual top-side marking has one additional character that designates the assembly/test site.  
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas  
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
PRODUCTION DATA information is current as of publication date.  
Copyright © 2005–2009, Texas Instruments Incorporated  
Products conform to specifications per the terms of the Texas  
Instruments standard warranty. Production processing does not  
necessarily include testing of all parameters.  
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