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SN74LVC1G79DBVRG4 PDF预览

SN74LVC1G79DBVRG4

更新时间: 2024-09-29 15:52:19
品牌 Logo 应用领域
德州仪器 - TI 光电二极管输出元件逻辑集成电路触发器
页数 文件大小 规格书
20页 1020K
描述
LVC/LCX/Z SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, PDSO5, GREEN, PLASTIC, SOT-23, 5 PIN

SN74LVC1G79DBVRG4 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Obsolete零件包装代码:SOT-23
包装说明:LSSOP, TSOP5/6,.11,37针数:5
Reach Compliance Code:unknownECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:5.07
系列:LVC/LCX/ZJESD-30 代码:R-PDSO-G5
JESD-609代码:e4长度:2.9 mm
负载电容(CL):50 pF逻辑集成电路类型:D FLIP-FLOP
最大I(ol):0.024 A湿度敏感等级:1
位数:1功能数量:1
端子数量:5最高工作温度:85 °C
最低工作温度:-40 °C输出特性:3-STATE
输出极性:TRUE封装主体材料:PLASTIC/EPOXY
封装代码:LSSOP封装等效代码:TSOP5/6,.11,37
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, LOW PROFILE, SHRINK PITCH
包装方法:TR峰值回流温度(摄氏度):260
电源:3.3 VProp。Delay @ Nom-Sup:5 ns
传播延迟(tpd):20.5 ns认证状态:Not Qualified
座面最大高度:1.45 mm子类别:FF/Latches
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):1.65 V
标称供电电压 (Vsup):1.8 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子面层:Nickel/Palladium/Gold (Ni/Pd/Au)端子形式:GULL WING
端子节距:0.95 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED触发器类型:POSITIVE EDGE
宽度:1.6 mm最小 fmax:160 MHz
Base Number Matches:1

SN74LVC1G79DBVRG4 数据手册

 浏览型号SN74LVC1G79DBVRG4的Datasheet PDF文件第2页浏览型号SN74LVC1G79DBVRG4的Datasheet PDF文件第3页浏览型号SN74LVC1G79DBVRG4的Datasheet PDF文件第4页浏览型号SN74LVC1G79DBVRG4的Datasheet PDF文件第5页浏览型号SN74LVC1G79DBVRG4的Datasheet PDF文件第6页浏览型号SN74LVC1G79DBVRG4的Datasheet PDF文件第7页 
SN74LVC1G79  
SINGLE POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP  
www.ti.com  
SCES220SAPRIL 1999REVISED NOVEMBER 2007  
1
FEATURES  
2
Available in the Texas Instruments NanoFree™  
Package  
Latch-Up Performance Exceeds 100 mA Per  
JESD 78, Class II  
Supports 5-V VCC Operation  
Inputs Accept Voltages to 5.5 V  
Max tpd of 4 ns at 3.3 V  
ESD Protection Exceeds JESD 22  
2000-V Human-Body Model (A114-A)  
200-V Machine Model (A115-A)  
Low Power Consumption, 10-µA Max ICC  
±24-mA Output Drive at 3.3 V  
1000-V Charged-Device Model (C101)  
Ioff Supports Partial-Power-Down Mode  
Operation  
DBV PACKAGE  
(TOP VIEW)  
DCK PACKAGE  
(TOP VIEW)  
DRL PACKAGE  
(TOP VIEW)  
YZP PACKAGE  
(BOTTOM VIEW)  
3
2
1
4
GND  
CLK  
D
Q
VCC  
1
2
3
5
VCC  
D
CLK  
GND  
1
2
3
5
D
CLK  
GND  
VCC  
1
2
3
5
4
D
CLK  
5
VCC  
4
Q
4
Q
GND  
Q
See mechanical drawings for dimensions.  
DESCRIPTION/ORDERING INFORMATION  
This single positive-edge-triggered D-type flip-flop is designed for 1.65-V to 5.5-V VCC operation.  
When data at the data (D) input meets the setup time requirement, the data is transferred to the Q output on the  
positive-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not directly related to the  
rise time of the clock pulse. Following the hold-time interval, data at the D input can be changed without affecting  
the level at the output.  
NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the die as the  
package.  
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs,  
preventing damaging current backflow through the device when it is powered down.  
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
2
NanoFree is a trademark of Texas Instruments.  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of the Texas  
Instruments standard warranty. Production processing does not  
necessarily include testing of all parameters.  
Copyright © 1999–2007, Texas Instruments Incorporated  

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