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ꢀꢊ ꢁꢈ ꢄ ꢋ ꢌꢍꢎ ꢏꢐ ꢋ ꢄꢑꢎꢆ ꢒ
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SCES528A − DECEMBER 2003 − REVISED JUNE 2004
DBV OR DCK PACKAGE
(TOP VIEW)
D
Available in the Texas Instruments
NanoStar and NanoFree Packages
D
D
D
D
D
D
D
D
Supports 5-V V
Operation
CC
1
2
3
6
5
4
LE
GND
D
OE
Inputs Accept Voltages to 5.5 V
V
CC
Max t of 4 ns at 3.3 V
pd
Low Power Consumption, 10-µA Max I
24-mA Output Drive at 3.3 V
Q
CC
YEP OR YZP PACKAGE
(BOTTOM VIEW)
I
Supports Partial-Power-Down Mode
off
Operation
3 4
2 5
1 6
D
GND
LE
Q
Latch-Up Performance Exceeds 100 mA
Per JESD 78, Class II
V
CC
OE
ESD Protection Exceeds JESD 22
− 2000-V Human-Body Model (A114-A)
− 200-V Machine Model (A115-A)
− 1000-V Charged-Device Model (C101)
description/ordering information
This single D-type latch is designed for 1.65-V to 5.5-V V
operation.
CC
The SN74LVC1G373 is particularly suitable for implementing buffer registers, I/O ports, bidirectional bus
drivers, and working registers. While the latch-enable (LE) input is high, the Q outputs follow the data (D) inputs.
When LE is taken low, the Q outputs are latched at the logic levels set up at the D inputs.
While the latch-enable (LE) input is high, the Q output follows the data (D) input. When LE is taken low, the Q
output is latched at the logic level set up at the D input.
NanoStar and NanoFree package technology is a major breakthrough in IC packaging concepts, using the
die as the package.
OE does not affect the internal operations of the latch. Old data can be retained or new data can be entered
while the outputs are in the high-impedance state.
ORDERING INFORMATION
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
†
T
A
PACKAGE
‡
NanoStar − WCSP (DSBGA)
0.23-mm Large Bump − YEP
SN74LVC1G373YEPR
SN74LVC1G373YZPR
Reel of 3000
_ _ _D3_
NanoFree − WCSP (DSBGA)
0.23-mm Large Bump − YZP (Pb-free)
−40°C to 85°C
Reel of 3000
Reel of 250
Reel of 3000
SN74LVC1G373DBVR
SN74LVC1G373DBVT
SN74LVC1G373DCKR
SOT (SOT-23) − DBV
CA3_
D3_
SOT (SC-70) − DCK
Reel of 250
SN74LVC1G373DCKT
†
‡
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.
DBV/DCK: The actual top-side marking has one additional character that designates the assembly/test site.
YEP/YZP: The actual top-side marking has three preceding characters to denote year, month, and sequence code, and one
following character to designate the assembly/test site. Pin
1 identifier indicates solder-bump composition
(1 = SnPb, • = Pb-free).
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
NanoStar and NanoFree are trademarks of Texas Instruments.
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Copyright 2004, Texas Instruments Incorporated
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