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SN74LVC1G38DBVRG4 PDF预览

SN74LVC1G38DBVRG4

更新时间： 2024-11-25 11:07:11
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德州仪器 - TI 栅栅极
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12页 261K
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具有漏极开路输出的单路 2 输入、1.65V 至 5.5V 与非门 | DBV | 5 | -40 to 125

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SN74LVC1G38DBVRG4 数据手册

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SN74LVC1G38  
SINGLE 2-INPUT NAND GATE  
WITH OPEN-DRAIN OUTPUT  
www.ti.com  
SCES538A–JANUARY 2004–REVISED APRIL 2005  
FEATURES  
DBV OR DCK PACKAGE  
(TOP VIEW)  
•
Available in the Texas Instruments  
NanoStar™ and NanoFree™ Packages  
1
2
3
5
4
A
B
V
Y
•
•
•
•
•
•
Supports 5-V VCC Operation  
CC  
Inputs Accept Voltages to 5.5 V  
Max tpd of 4.5 ns at 3.3 V  
GND  
Low Power Consumption, 10-µA Max ICC  
±24-mA Output Drive at 3.3 V  
YEP OR YZP PACKAGE  
(BOTTOM VIEW)  
Ioff Supports Partial-Power-Down Mode  
Operation  
3
2
1
4
5
GND  
B
Y
V
•
•
Latch-Up Performance Exceeds 100 mA Per  
JESD 78, Class II  
A
CC  
ESD Protection Exceeds JESD 22  
– 2000-V Human-Body Model (A114-A)  
– 200-V Machine Model (A115-A)  
– 1000-V Charged-Device Model (C101)  
DESCRIPTION/ORDERING INFORMATION  
The SN74LVC1G38 is designed for 1.65-V to 5.5-V VCC operation.  
This device is a single two-input NAND buffer gate with open-drain output. It performs the Boolean function  
Y = A B or Y = A + B in positive logic.  
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs,  
preventing damaging current backflow through the device when it is powered down.  
NanoStar™ and NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the  
die as the package.  
ORDERING INFORMATION  
TA  
PACKAGE(1)  
NanoStar™ – WCSP (DSBGA)  
ORDERABLE PART NUMBER  
TOP-SIDE MARKING(2)  
SN74LVC1G38YEPR  
0.23-mm Large Bump – YEP  
Reel of 3000  
_ _ _D7_  
NanoFree™ – WCSP (DSBGA)  
0.23-mm Large Bump – YZP (Pb-free)  
SN74LVC1G38YZPR  
–40°C to 85°C  
Reel of 3000 SN74LVC1G38DBVR  
Reel of 250 SN74LVC1G38DBVT  
Reel of 3000 SN74LVC1G38DCKR  
Reel of 250 SN74LVC1G38DCKT  
SOT (SOT-23) – DBV  
SOT (SC-70) – DCK  
C38_  
D7_  
(1) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at  
www.ti.com/sc/package.  
(2) DBV/DCK: The actual top-side marking has one additional character that designates the assembly/test site.  
YEP/YZP: The actual top-side marking has three preceding characters to denote year, month, and sequence code, and one following  
character to designate the assembly/test site. Pin 1 identifier indicates solder-bump composition (1 = SnPb, = Pb-free).  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas  
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
NanoStar, NanoFree are trademarks of Texas Instruments.  
PRODUCTION DATA information is current as of publication date.  
Copyright © 2004–2005, Texas Instruments Incorporated  
Products conform to specifications per the terms of the Texas  
Instruments standard warranty. Production processing does not  
necessarily include testing of all parameters.  
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SN74LVC1G38DBVRG4 替代型号

型号 品牌 替代类型 描述 数据表
SN74LVC1G38DBVTG4 TI

完全替代

 具有漏极开路输出的单路 2 输入、1.65V 至 5.5V 与非门 | DBV | 5 |
SN74LVC1G38DBVR TI

类似代替

 SINGLE 2-INPUT NAND GATE WITH OPEN-DRAIN OUTPUT

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 		具有漏极开路输出的单路 2 输入、1.65V 至 5.5V 与非门 | DCK | 5 |
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 		SINGLE 2-INPUT NAND GATE WITH OPEN-DRAIN OUTPUT
SN74LVC1G38DCKTE4 TI

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 		Single 2-Input NAND Gate with Open Drain Output 5-SC70 -40 to 85
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 		具有漏极开路输出的单路 2 输入、1.65V 至 5.5V 与非门 | DPW | 5 |
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 		具有漏极开路输出的单路 2 输入、1.65V 至 5.5V 与非门 | DRY | 6 |
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