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SN74LVC1G132_07

更新时间： 2024-11-05 05:29:35
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德州仪器 - TI 触发器输入元件
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SINGLE 2-INPUT NAND GATE WITH SCHMITT-TRIGGER INPUTS

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SN74LVC1G132_07 数据手册

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SN74LVC1G132  
SINGLE 2-INPUT NAND GATE  
WITH SCHMITT-TRIGGER INPUTS  
www.ti.com  
SCES546B–FEBRUARY 2004–REVISED SEPTEMBER 2006  
FEATURES  
•
•
•
Ioff Supports Partial-Power-Down Mode  
Operation  
•
Available in Texas Instruments NanoStar™  
and NanoFree™ Packages  
Latch-Up Performance Exceeds 100 mA Per  
JESD 78, Class II  
•
•
•
•
•
Supports 5-V VCC Operation  
ESD Protection Exceeds JESD 22  
– 2000-V Human-Body Model (A114-A)  
– 200-V Machine Model (A115-A)  
Inputs Accept Voltages to 5.5 V  
Max tpd of 5.3 ns at 3.3 V  
Low Power Consumption, 10-µA Max ICC  
±24-mA Output Drive at 3.3 V  
– 1000-V Charged-Device Model (C101)  
DBV PACKAGE  
(TOP VIEW)  
DCK PACKAGE  
(TOP VIEW)  
YEP OR YZP PACKAGE  
(BOTTOM VIEW)  
3
2
1
4
5
GND  
B
Y
VCC  
1
2
3
5
A
B
VCC  
1
2
3
5
4
A
B
VCC  
A
4
GND  
Y
GND  
Y
See mechanical drawings for dimensions.  
DESCRIPTION/ORDERING INFORMATION  
The SN74LVC1G132 contains one 2-input NAND gate with Schmitt-trigger inputs designed for 1.65-V to 5.5-V  
VCC operation and performs the Boolean function Y = A • B or Y = A + B in positive logic.  
Because of Schmitt action, this device has different input threshold levels for positive-going (VT+) and  
negative-going (VT–) signals.  
This device can be triggered from the slowest of input ramps and still give clean jitter-free output signals.  
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs,  
preventing damaging current backflow through the device when it is powered down.  
NanoStar™ and NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the  
die as the package.  
ORDERING INFORMATION  
TA  
PACKAGE(1)  
ORDERABLE PART NUMBER  
TOP-SIDE MARKING(2)  
NanoStar™ – WCSP (DSBGA)  
0.23-mm Large Bump – YEP  
SN74LVC1G132YEPR  
Reel of 3000  
_ _ _D5_  
NanoFree™ – WCSP (DSBGA)  
0.23-mm Large Bump – YZP  
(Pb-free)  
SN74LVC1G132YZPR  
–40°C to 85°C  
Reel of 3000  
Reel of 250  
Reel of 3000  
Reel of 250  
SN74LVC1G132DBVR  
SN74LVC1G132DBVT  
SN74LVC1G132DCKR  
SN74LVC1G132DCKT  
SOT (SOT-23) – DBV  
SOT (SC-70) – DCK  
C3B_  
D5_  
(1) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at  
www.ti.com/sc/package.  
(2) DBV/DCK: The actual top-side marking has one additional character that designates the assembly/test site.  
YEP/YZP: The actual top-side marking has three preceding characters to denote year, month, and sequence code, and one following  
character to designate the assembly/test site. Pin 1 identifier indicates solder-bump composition (1 = SnPb, • = Pb-free).  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas  
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
NanoStar, NanoFree are trademarks of Texas Instruments.  
PRODUCTION DATA information is current as of publication date.  
Copyright © 2004–2006, Texas Instruments Incorporated  
Products conform to specifications per the terms of the Texas  
Instruments standard warranty. Production processing does not  
necessarily include testing of all parameters.  
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