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SN74LVC1G139YEPR PDF预览

SN74LVC1G139YEPR

更新时间： 2024-11-17 22:13:47
品牌 Logo 应用领域
德州仪器 - TI /
页数 文件大小 规格书
10页 146K
描述
2-TO -4 LINE DECODER

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中文翻译

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SN74LVC1G139YEPR 技术参数

生命周期：Obsolete零件包装代码：BGA
包装说明：VFBGA, BGA8,2X4,20针数：8
Reach Compliance Code：unknownECCN代码：EAR99
HTS代码：8542.39.00.01风险等级：5.65
其他特性：TXIIK01155系列：LVC/LCX/Z
输入调节：STANDARDJESD-30 代码：R-XBGA-B8
长度：1.9 mm负载电容（CL）：50 pF
逻辑集成电路类型：OTHER DECODER/DRIVER最大I（ol）：0.024 A
功能数量：1端子数量：8
最高工作温度：85 °C最低工作温度：-40 °C
输出特性：3-STATE输出极性：INVERTED
封装主体材料：UNSPECIFIED封装代码：VFBGA
封装等效代码：BGA8,2X4,20封装形状：RECTANGULAR
封装形式：GRID ARRAY, VERY THIN PROFILE, FINE PITCH包装方法：TAPE AND REEL
电源：3.3 VProp。Delay @ Nom-Sup：5.9 ns
传播延迟（tpd）：16.7 ns认证状态：Not Qualified
座面最大高度：0.5 mm子类别：Decoder/Drivers
最大供电电压 (Vsup)：5.5 V最小供电电压 (Vsup)：1.65 V
标称供电电压 (Vsup)：1.8 V表面贴装：YES
技术：CMOS温度等级：INDUSTRIAL
端子形式：BALL端子节距：0.5 mm
端子位置：BOTTOM宽度：0.9 mm

SN74LVC1G139YEPR 数据手册

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SCES602 − AUGUST 2004  
DCT OR DCU PACKAGE  
(TOP VIEW)  
D
Available in the Texas Instruments  
NanoStarand NanoFreePackages  
D
D
D
D
D
D
D
D
Supports 5-V V  
Operation  
CC  
V
1
2
3
4
8
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5
A
B
CC  
Inputs Accept Voltages to 5.5 V  
Y0  
Y1  
Y2  
Y3  
GND  
Max t of 4.9 ns at 3.3 V  
pd  
Low Power Consumption, 10-µA Max I  
24-mA Output Drive at 3.3 V  
CC  
YEP OR YZP PACKAGE  
(BOTTOM VIEW)  
I
Supports Partial-Power-Down Mode  
off  
Operation  
4 5  
3 6  
2 7  
1 8  
GND  
Y3  
B
Y2  
Y1  
Y0  
Latch-Up Performance Exceeds 100 mA  
Per JESD 78, Class II  
ESD Protection Exceeds JESD 22  
− 2000-V Human-Body Model (A114-A)  
− 200-V Machine Model (A115-A)  
− 1000-V Charged-Device Model (C101)  
A
V
CC  
description/ordering information  
This 2-to-4 line decoder is designed for 1.65-V to 5.5-V V  
operation.  
CC  
The SN74LVC1G139 2-line to 4-line decoder is designed to be used in high-performance memory-decoding  
or data-routing applications requiring very short propagation delay times. In high-performance memory  
systems, this decoder can be used to minimize the effects of system decoding. When used with high-speed  
memories utilizing a fast enable circuit, the delay times of these decoders and the enable time of the memory  
usually are less than the typical access time of the memory. This means that the effective system delay  
introduced by the decoder is negligible.  
NanoStarand NanoFreepackage technology is a major breakthrough in IC packaging concepts, using the  
die as the package.  
ORDERING INFORMATION  
ORDERABLE  
PART NUMBER  
TOP-SIDE  
MARKING  
†
T
A
PACKAGE  
‡
NanoStar− WCSP (DSBGA)  
0.23-mm Large Bump − YEP  
SN74LVC1G139YEPR  
SN74LVC1G139YZPR  
Reel of 3000  
_ _ _C9_  
NanoFree− WCSP (DSBGA)  
0.23-mm Large Bump − YZP (Pb-free)  
−40°C to 85°C  
Reel of 3000  
Reel of 250  
Reel of 3000  
SN74LVC1G139DCTR  
SN74LVC1G139DCTT  
SN74LVC1G139DCUR  
SSOP − DCT  
C39_ _ _  
C39_  
VSSOP − DCU  
Reel of 250  
SN74LVC1G139DCUT  
†
‡
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at  
www.ti.com/sc/package.  
DCT: The actual top-side marking has three additional characters that designate the year, month, and assembly/test site.  
DCU: The actual top-side marking has one additional character that designates the assembly/test site.  
YEP/YZP: The actual top-side marking has three preceding characters to denote year, month, and sequence code, and one  
following character to designate the assembly/test site. Pin  
1 identifier indicates solder-bump composition  
(1 = SnPb, • = Pb-free).  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
NanoStar and NanoFree are trademarks of Texas Instruments.  
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Copyright 2004 Texas Instruments Incorporated  
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1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567...10

中文翻译

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