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SN74LVC1G132DBVT PDF预览

SN74LVC1G132DBVT

更新时间: 2024-09-14 23:11:03
品牌 Logo 应用领域
德州仪器 - TI 栅极触发器逻辑集成电路光电二极管输入元件PC
页数 文件大小 规格书
13页 269K
描述
SINGLE 2-INPUT NAND GATE WITH SCHMITT-TRIGGER INPUTS

SN74LVC1G132DBVT 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Active零件包装代码:SOT-23
包装说明:LSSOP, TSOP5/6,.11,37针数:5
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:1.15
Samacsys Confidence:3Samacsys Status:Released
Samacsys PartID:289762Samacsys Pin Count:5
Samacsys Part Category:Integrated CircuitSamacsys Package Category:SOT23 (5-Pin)
Samacsys Footprint Name:DBV0005ASamacsys Released Date:2018-05-29 06:46:00
Is Samacsys:N系列:LVC/LCX/Z
JESD-30 代码:R-PDSO-G5JESD-609代码:e4
长度:2.9 mm负载电容(CL):50 pF
逻辑集成电路类型:NAND GATE最大I(ol):0.032 A
湿度敏感等级:1功能数量:1
输入次数:2端子数量:5
最高工作温度:125 °C最低工作温度:-40 °C
输出特性:3-STATE封装主体材料:PLASTIC/EPOXY
封装代码:LSSOP封装等效代码:TSOP5/6,.11,37
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, LOW PROFILE, SHRINK PITCH
包装方法:TR峰值回流温度(摄氏度):260
电源:3.3 V最大电源电流(ICC):0.01 mA
Prop。Delay @ Nom-Sup:6 ns传播延迟(tpd):16 ns
认证状态:Not Qualified施密特触发器:YES
座面最大高度:1.45 mm子类别:Gates
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):1.65 V
标称供电电压 (Vsup):1.8 V表面贴装:YES
技术:CMOS温度等级:AUTOMOTIVE
端子面层:Nickel/Palladium/Gold (Ni/Pd/Au)端子形式:GULL WING
端子节距:0.95 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:1.6 mm
Base Number Matches:1

SN74LVC1G132DBVT 数据手册

 浏览型号SN74LVC1G132DBVT的Datasheet PDF文件第2页浏览型号SN74LVC1G132DBVT的Datasheet PDF文件第3页浏览型号SN74LVC1G132DBVT的Datasheet PDF文件第4页浏览型号SN74LVC1G132DBVT的Datasheet PDF文件第5页浏览型号SN74LVC1G132DBVT的Datasheet PDF文件第6页浏览型号SN74LVC1G132DBVT的Datasheet PDF文件第7页 
ꢀꢁ ꢂꢃ ꢄꢅ ꢆꢇ ꢈ ꢇꢉ ꢊ  
ꢀꢋ ꢁꢈ ꢄ ꢌ ꢊ ꢍꢋꢁ ꢎꢏꢐ ꢁꢑꢁ ꢒ ꢈ ꢑꢐꢌ  
ꢓ ꢋꢐ ꢔ ꢀꢆꢔ ꢕꢋ ꢐꢐꢍꢐ ꢖꢋꢈ ꢈ ꢌꢖ ꢋ ꢁꢎ ꢏ ꢐꢀ  
SCES546A − FEBRUARY 2004 − REVISED AUGUST 2004  
DBV OR DCK PACKAGE  
(TOP VIEW)  
D
Available in Texas Instruments NanoStar  
and NanoFreePackages  
D
D
D
D
D
D
D
D
Supports 5-V V  
Operation  
CC  
1
2
3
5
4
A
B
GND  
V
Y
CC  
Inputs Accept Voltages to 5.5 V  
Max t of 5.3 ns at 3.3 V  
pd  
Low Power Consumption, 10-µA Max I  
CC  
YEP OR YZP PACKAGE  
(BOTTOM VIEW)  
24-mA Output Drive at 3.3 V  
I
Supports Partial-Power-Down Mode  
off  
Operation  
3 4  
2
GND  
B
Y
V
Latch-Up Performance Exceeds 100 mA Per  
JESD 78, Class II  
1 5  
A
CC  
ESD Protection Exceeds JESD 22  
− 2000-V Human-Body Model (A114-A)  
− 200-V Machine Model (A115-A)  
− 1000-V Charged-Device Model (C101)  
description/ordering information  
The SN74LVC1G132 contains one 2-input NAND gate with Schmitt-trigger inputs designed for 1.65-V to 5.5-V  
operation and performs the Boolean function Y = A B or Y = A + B in positive logic.  
V
CC  
Because of Schmitt action, this device has different input threshold levels for positive-going (V ) and  
T+  
negative-going (V ) signals.  
T−  
This device can be triggered from the slowest of input ramps and still give clean jitter-free output signals.  
This device is fully specified for partial-power-down applications using I . The I circuitry disables the outputs,  
off  
off  
preventing damaging current backflow through the device when it is powered down.  
NanoStarand NanoFreepackage technology is a major breakthrough in IC packaging concepts, using the  
die as the package.  
ORDERING INFORMATION  
ORDERABLE  
PART NUMBER  
TOP-SIDE  
MARKING  
T
A
PACKAGE  
NanoStar− WCSP (DSBGA)  
0.23-mm Large Bump − YEP  
SN74LVC1G132YEPR  
SN74LVC1G132YZPR  
Reel of 3000  
_ _ _D5_  
NanoFree− WCSP (DSBGA)  
0.23-mm Large Bump − YZP (Pb-free)  
−40°C to 85°C  
Reel of 3000  
Reel of 250  
Reel of 3000  
Reel of 250  
SN74LVC1G132DBVR  
SN74LVC1G132DBVT  
SN74LVC1G132DCKR  
SN74LVC1G132DCKT  
SOT (SOT-23) − DBV  
C3B_  
D5_  
SOT (SC-70) − DCK  
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at  
www.ti.com/sc/package.  
DBV/DCK: The actual top-side marking has one additional character that designates the assembly/test site.  
YEP/YZP: The actual top-side marking has three preceding characters to denote year, month, and sequence code, and one  
following character to designate the assembly/test site. Pin  
1 identifier indicates solder-bump composition  
(1 = SnPb, = Pb-free).  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
NanoStar and NanoFree are trademarks of Texas Instruments.  
ꢐꢣ  
Copyright 2004, Texas Instruments Incorporated  
ꢟ ꢣ ꢠ ꢟꢘ ꢙꢭ ꢛꢚ ꢞ ꢦꢦ ꢤꢞ ꢜ ꢞ ꢝ ꢣ ꢟ ꢣ ꢜ ꢠ ꢨ  
1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  

SN74LVC1G132DBVT 替代型号

型号 品牌 替代类型 描述 数据表
SN74LVC1G132DBVTG4 TI

完全替代

SINGLE 2-INPUT NAND GATE WITH SCHMITT-TRIGGER INPUTS
SN74LVC1G132DBVTE4 TI

完全替代

SINGLE 2-INPUT NAND GATE WITH SCHMITT-TRIGGER INPUTS
74LVC1G132DBVTE4 TI

完全替代

SINGLE 2-INPUT NAND GATE WITH SCHMITT-TRIGGER INPUTS

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