SN54LV123A, SN74LV123A
DUAL RETRIGGERABLE MONOSTABLE MULTIVIBRATORS
WITH SCHMITT-TRIGGER INPUTS
SCLS393A – APRIL 1998 – REVISED DECEMBER 1999
SN54LV123A . . . J OR W PACKAGE
SN74LV123A . . . D, DB, DGV, NS, OR PW PACKAGE
(TOP VIEW)
EPIC (Enhanced-Performance Implanted
CMOS) Process
Schmitt-Trigger Circuitry on A, B, and CLR
Inputs for Slow Input Transition Rates
1A
1B
V
CC
1
2
3
4
5
6
7
8
16
15
14
13
1R /C
Edge Triggered From Active-High or
Active-Low Gated Logic Inputs
ext ext
1CLR
1Q
1C
1Q
ext
Retriggerable for Very Long Output Pulses,
up to 100% Duty Cycle
2Q
12 2Q
11
10
9
2C
2CLR
2B
ext
Overriding Clear Terminates Output Pulse
Glitch-Free Power-Up Reset on Outputs
2R /C
ext ext
GND
2A
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
SN54LV123A . . . FK PACKAGE
(TOP VIEW)
ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)
Package Options Include Plastic
Small-Outline (D, NS), Shrink Small-Outline
(DB), Thin Very Small-Outline (DGV), and
Thin Shrink Small-Outline (PW) Packages,
Ceramic Flat (W) Packages, Chip Carriers
(FK), and DIPs (J)
3
2
1 20 19
18
1C
1Q
1CLR
1Q
4
5
6
7
8
ext
17
16
NC
NC
15 2Q
14
9 10 11 12 13
2Q
2CLR
2C
ext
description
The ’LV123A devices are dual retriggerable
monostable multivibrators designed for 2-V to
5.5-V V
operation.
CC
These edge-triggered multivibrators feature
output pulse-duration control by three methods. In
the first method, the A input is low and the B input
goes high. In the second method, the B input is
high and the A input goes low. In the third method,
the A input is low, the B input is high, and the clear
(CLR) input goes high.
NC – No internal connection
The output pulse duration is programmable by selecting external resistance and capacitance values. The
external timing capacitor must be connected between C and R /C (positive) and an external resistor
ext
ext ext
connected between R /C
and V . To obtain variable pulse durations, connect an external variable
ext ext
CC
resistance between R /C and V . The output pulse duration can also be reduced by taking CLR low.
ext ext
CC
Pulse triggering occurs at a particular voltage level and is not directly related to the transition time of the input
pulse. The A, B, and CLR inputs have Schmitt triggers with sufficient hysteresis to handle slow input transition
rates with jitter-free triggering at the outputs.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC is a trademark of Texas Instruments Incorporated.
Copyright 1999, Texas Instruments Incorporated
UNLESS OTHERWISE NOTED this document contains PRODUCTION
DATA information current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all
parameters.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265