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SN74LV123A-Q1 PDF预览

SN74LV123A-Q1

更新时间: 2024-02-16 01:57:52
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德州仪器 - TI 触发器输入元件
页数 文件大小 规格书
10页 164K
描述
DUAL RETRIGGERABLE MONOSTABLE MULTIVIBRATOR WITH SCHMITT - TRIGGER INPUTS

SN74LV123A-Q1 数据手册

 浏览型号SN74LV123A-Q1的Datasheet PDF文件第2页浏览型号SN74LV123A-Q1的Datasheet PDF文件第3页浏览型号SN74LV123A-Q1的Datasheet PDF文件第4页浏览型号SN74LV123A-Q1的Datasheet PDF文件第5页浏览型号SN74LV123A-Q1的Datasheet PDF文件第6页浏览型号SN74LV123A-Q1的Datasheet PDF文件第7页 
ꢀꢁ ꢂꢃ ꢄꢅ ꢆꢇ ꢈꢉ ꢊꢋ ꢆ  
ꢌ ꢍꢉꢄ ꢎꢏ ꢐꢎꢑ ꢒ ꢒꢏ ꢎꢉꢓꢄ ꢏ ꢔ ꢕꢁ ꢕꢀ ꢐꢉꢓꢄ ꢏ ꢔ ꢍꢄꢐ ꢑꢅ ꢑ ꢓꢎ ꢉꢐꢕ ꢎ  
ꢖ ꢑꢐ ꢗ ꢀꢘ ꢗꢔꢑ ꢐꢐꢊꢐ ꢎꢑꢒ ꢒ ꢏ ꢎ ꢑ ꢁꢙ ꢍ ꢐꢀ  
SCLS467B − FEBRUARY 2003 − REVISED MAY 2004  
PW PACKAGE  
(TOP VIEW)  
D
Qualification in Accordance With  
AEC-Q100  
D
Qualified for Automotive Applications  
1A  
1B  
V
CC  
1
2
3
4
5
6
7
8
16  
15  
14  
13  
D
Customer-Specific Configuration Control  
Can Be Supported Along With  
Major-Change Approval  
1R /C  
ext ext  
1CLR  
1Q  
1C  
1Q  
ext  
2Q  
12 2Q  
D
D
D
D
D
D
D
Typical V  
<0.8 V at V  
(Output Ground Bounce)  
OLP  
CC  
11  
10  
9
2C  
ext  
2CLR  
2B  
= 3.3 V, T = 25°C  
A
2R /C  
ext ext  
GND  
Typical V  
>2.3 V at V  
(Output V  
Undershoot)  
OHV  
CC  
OH  
2A  
= 3.3 V, T = 25°C  
A
Supports Mixed-Mode Voltage Operation on  
All Ports  
Schmitt-Trigger Circuitry on A, B, and CLR  
Inputs for Slow Input Transition Rates  
Edge Triggered From Active-High or  
Active-Low Gated Logic Inputs  
I
Supports Partial-Power-Down Mode  
off  
Operation  
Retriggerable for Very Long Output Pulses,  
Up To 100% Duty Cycle  
D
D
D
Overriding Clear Terminates Output Pulse  
Glitch-Free Power-Up Reset on Outputs  
ESD Protection Exceeds JESD 22  
− 2000-V Human-Body Model (A114-A)  
− 200-V Machine Model (A115-A)  
− 1000-V Charged-Device Model (C101)  
Contact factory for details. Q100 qualification data available on  
request.  
description/ordering information  
The SN74LV123A is a dual retriggerable monostable multivibrator designed for 2-V to 5.5-V V  
operation.  
CC  
This edge-triggered multivibrator features output pulse-duration control by three methods. In the first method,  
the A input is low, and the B input goes high. In the second method, the B input is high, and the A input goes  
low. In the third method, the A input is low, the B input is high, and the clear (CLR) input goes high.  
The output pulse duration is programmable by selecting external resistance and capacitance values. The  
external timing capacitor must be connected between C  
and R /C  
(positive) and an external resistor  
ext  
ext ext  
connected between R /C  
resistance between R /C and V . The output pulse duration also can be reduced by taking CLR low.  
and V . To obtain variable pulse durations, connect an external variable  
ext ext  
CC  
ext ext  
CC  
ORDERING INFORMATION  
ORDERABLE  
PART NUMBER  
TOP-SIDE  
MARKING  
T
PACKAGE  
TSSOP − PW  
A
−40°C to 105°C  
Tape and reel SN74LV123ATPWRQ1 L123ATQ  
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design  
guidelines are available at www.ti.com/sc/package.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
ꢐꢥ  
Copyright 2004, Texas Instruments Incorporated  
ꢡ ꢥ ꢢ ꢡꢚ ꢛꢯ ꢝꢜ ꢠ ꢨꢨ ꢦꢠ ꢞ ꢠ ꢟ ꢥ ꢡ ꢥ ꢞ ꢢ ꢪ  
1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  

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