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SN74LV125ADG4 PDF预览

SN74LV125ADG4

更新时间: 2024-11-04 09:13:39
品牌 Logo 应用领域
德州仪器 - TI 总线驱动器总线收发器逻辑集成电路光电二极管输出元件
页数 文件大小 规格书
21页 779K
描述
QUADRUPLE BUS BUFFER GATES WITH 3-STATE OUTPUTS

SN74LV125ADG4 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Active零件包装代码:SOIC
包装说明:SOP, SOP14,.25针数:14
Reach Compliance Code:compliantHTS代码:8542.39.00.01
Factory Lead Time:6 weeks风险等级:5.07
控制类型:ENABLE LOW计数方向:UNIDIRECTIONAL
系列:LV/LV-A/LVX/HJESD-30 代码:R-PDSO-G14
JESD-609代码:e4长度:8.65 mm
负载电容(CL):50 pF逻辑集成电路类型:BUS DRIVER
最大I(ol):0.016 A湿度敏感等级:1
位数:1功能数量:4
端口数量:2端子数量:14
最高工作温度:125 °C最低工作温度:-40 °C
输出特性:3-STATE输出极性:TRUE
封装主体材料:PLASTIC/EPOXY封装代码:SOP
封装等效代码:SOP14,.25封装形状:RECTANGULAR
封装形式:SMALL OUTLINE包装方法:TUBE
峰值回流温度(摄氏度):260电源:3.3 V
最大电源电流(ICC):0.02 mAProp。Delay @ Nom-Sup:13 ns
传播延迟(tpd):18.5 ns认证状态:Not Qualified
座面最大高度:1.75 mm子类别:Bus Driver/Transceivers
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):2 V
标称供电电压 (Vsup):2.5 V表面贴装:YES
技术:CMOS温度等级:AUTOMOTIVE
端子面层:Nickel/Palladium/Gold (Ni/Pd/Au)端子形式:GULL WING
端子节距:1.27 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:3.91 mm
Base Number Matches:1

SN74LV125ADG4 数据手册

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ꢀꢁ ꢂꢃ ꢄꢅꢆ ꢇ ꢂ ꢈꢉ ꢀꢁꢊ ꢃꢄꢅ ꢆꢇ ꢂꢈ  
ꢋ ꢌꢈꢍꢎ ꢌꢏꢄ ꢐ ꢑꢌꢀ ꢑꢌꢒ ꢒ ꢐꢎ ꢓ ꢈꢔꢐ ꢀ  
ꢕ ꢖꢔ ꢗ ꢘ ꢙꢀꢔꢈꢔ ꢐ ꢚ ꢌꢔ ꢏꢌ ꢔꢀ  
SCES124L − DECEMBER 1997 − REVISED APRIL 2005  
D
D
D
D
D
2-V to 5.5-V V  
Operation  
D
D
D
I
Supports Partial-Power-Down Mode  
CC  
off  
Operation  
Max t of 6 ns at 5 V  
pd  
Latch-Up Performance Exceeds 250 mA Per  
JESD 17  
Typical V  
<0.8 V at V  
(Output Ground Bounce)  
OLP  
CC  
= 3.3 V, T = 25°C  
A
ESD Protection Exceeds JESD 22  
− 2000-V Human-Body Model (A114-A)  
− 200-V Machine Model (A115-A)  
Typical V  
>2.3 V at V  
(Output V  
Undershoot)  
OHV  
CC  
OH  
= 3.3 V, T = 25°C  
A
Support Mixed-Mode Voltage Operation on  
All Ports  
− 1000-V Charged-Device Model (C101)  
SN54LV125A . . . J OR W PACKAGE  
SN74LV125A . . . D, DB, DGV, N, NS,  
OR PW PACKAGE  
SN74LV125A . . . RGY PACKAGE  
(TOP VIEW)  
SN54LV125A . . . FK PACKAGE  
(TOP VIEW)  
(TOP VIEW)  
1
14  
3
2
1
20 19  
18  
1OE  
1A  
V
CC  
13 4OE  
1
2
3
4
5
6
7
14  
4A  
NC  
4Y  
1Y  
NC  
4
5
6
7
8
1A  
1Y  
13 4OE  
12 4A  
2
3
4
5
6
17  
16  
12  
11  
10  
9
1Y  
4A  
2OE  
NC  
11  
10  
9
2OE  
2A  
4Y  
2OE  
2A  
4Y  
15 NC  
14  
9 10 11 12 13  
3OE  
3A  
3OE  
3A  
3OE  
2A  
2Y  
2Y  
7
8
8
GND  
3Y  
NC − No internal connection  
description/ordering information  
The ‘LV125A quadruple bus buffer gates are designed for 2-V to 5.5-V V  
operation.  
CC  
These devices feature independent line drivers with 3-state outputs. Each output is disabled when the  
associated output-enable (OE) input is high.  
ORDERING INFORMATION  
ORDERABLE  
PART NUMBER  
TOP-SIDE  
MARKING  
PACKAGE  
T
A
PDIP − N  
Tube of 25  
SN74LV125AN  
SN74LV125AN  
LV125A  
QFN − RGY  
Reel of 1000  
Tube of 50  
SN74LV125ARGYR  
SN74LV125AD  
SOIC − D  
LV125A  
Reel of 2500  
Reel of 2000  
Reel of 2000  
Tube of 90  
SN74LV125ADR  
SN74LV125ANSR  
SN74LV125ADBR  
SN74LV125APW  
SN74LV125APWR  
SN74LV125APWT  
SN74LV125ADGVR  
SNJ54LV125AJ  
SOP − NS  
74LV125A  
LV125A  
−40°C to 85°C  
SSOP − DB  
Reel of 2000  
Reel of 250  
Reel of 2000  
Tube of 25  
TSSOP − PW  
LV125A  
TVSOP − DGV  
CDIP − J  
LV125A  
SNJ54LV125AJ  
SNJ54LV125AW  
SNJ54LV125AFK  
−55°C to 125°C  
CFP − W  
Tube of 150  
Tube of 55  
SNJ54LV125AW  
SNJ54LV125AFK  
LCCC − FK  
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design  
guidelines are available at www.ti.com/sc/package.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Copyright 2005, Texas Instruments Incorporated  
ꢌ ꢁ ꢄꢐꢀꢀ ꢚ ꢔꢗ ꢐꢎꢕ ꢖꢀ ꢐ ꢁ ꢚꢔꢐꢍ ꢛꢜ ꢝꢞ ꢟꢠꢡ ꢢꢣꢤ ꢥꢛ ꢡꢠ ꢥꢛꢦ ꢝꢥꢞ ꢏꢎ ꢚ ꢍ ꢌ ꢧꢔ ꢖꢚ ꢁ  
ꢪꢦ ꢩ ꢦ ꢣ ꢤ ꢛ ꢤ ꢩ ꢞ ꢭ  
1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  

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