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SN74LV123APWTE4 PDF预览

SN74LV123APWTE4

更新时间： 2024-11-04 05:17:11
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德州仪器 - TI 触发器输入元件
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23页 531K
描述
DUAL RETRIGGERABLE MONOSTABLE MULTIVIBRATORS WITH SCHMITT-TRIGGER INPUTS

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SN74LV123APWTE4 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Obsolete零件包装代码：TSSOP
包装说明：TSSOP, TSSOP16,.25针数：16
Reach Compliance Code：unknownHTS代码：8542.39.00.01
风险等级：5.28其他特性：EDGE TRIGGERED FROM ACTIVE-HIGH OR ACTIVE-LOW GATED LOGIC INPUTS
系列：LV/LV-A/LVX/HJESD-30 代码：R-PDSO-G16
JESD-609代码：e4长度：5 mm
逻辑集成电路类型：MONOSTABLE MULTIVIBRATOR湿度敏感等级：1
数据/时钟输入次数：2功能数量：2
端子数量：16最高工作温度：85 °C
最低工作温度：-40 °C输出极性：COMPLEMENTARY
封装主体材料：PLASTIC/EPOXY封装代码：TSSOP
封装等效代码：TSSOP16,.25封装形状：RECTANGULAR
封装形式：SMALL OUTLINE, THIN PROFILE, SHRINK PITCH峰值回流温度（摄氏度）：260
电源：2.5/5 V传播延迟（tpd）：42 ns
认证状态：Not Qualified座面最大高度：1.2 mm
子类别：Prescaler/Multivibrators最大供电电压 (Vsup)：5.5 V
最小供电电压 (Vsup)：2 V标称供电电压 (Vsup)：2.5 V
表面贴装：YES技术：CMOS
温度等级：INDUSTRIAL端子面层：Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式：GULL WING端子节距：0.65 mm
端子位置：DUAL处于峰值回流温度下的最长时间：NOT SPECIFIED
宽度：4.4 mmBase Number Matches：1

SN74LV123APWTE4 数据手册

 浏览型号SN74LV123APWTE4的Datasheet PDF文件第2页浏览型号SN74LV123APWTE4的Datasheet PDF文件第3页浏览型号SN74LV123APWTE4的Datasheet PDF文件第4页浏览型号SN74LV123APWTE4的Datasheet PDF文件第5页浏览型号SN74LV123APWTE4的Datasheet PDF文件第6页浏览型号SN74LV123APWTE4的Datasheet PDF文件第7页 
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SCLS393O − APRIL 1998 − REVISED OCTOBER 2005  
D
D
D
D
D
D
D
2-V to 5.5-V V  
Operation  
D
D
D
D
D
I
Supports Partial-Power-Down Mode  
CC  
off  
Operation  
Max t of 11 ns at 5 V  
pd  
Retriggerable for Very Long Output Pulses,  
up to 100% Duty Cycle  
Typical V  
<0.8 V at V  
(Output Ground Bounce)  
OLP  
CC  
= 3.3 V, T = 25°C  
A
Overriding Clear Terminates Output Pulse  
Glitch-Free Power-Up Reset on Outputs  
Typical V  
>2.3 V at V  
(Output V  
Undershoot)  
OHV  
CC  
OH  
= 3.3 V, T = 25°C  
A
Support Mixed-Mode Voltage Operation on  
All Ports  
Latch-Up Performance Exceeds 100 mA Per  
JESD 78, Class II  
Schmitt-Trigger Circuitry on A, B, and CLR  
Inputs for Slow Input Transition Rates  
D
ESD Protection Exceeds JESD 22  
− 2000-V Human-Body Model (A114-A)  
− 200-V Machine Model (A115-A)  
Edge Triggered From Active-High or  
Active-Low Gated Logic Inputs  
− 1000-V Charged-Device Model (C101)  
SN74LV123A . . . RGY PACKAGE  
(TOP VIEW)  
SN54LV123A . . . FK PACKAGE  
(TOP VIEW)  
SN54LV123A . . . J OR W PACKAGE  
SN74LV123A . . . D, DB, DGV, NS,  
OR PW PACKAGE  
(TOP VIEW)  
1
16  
1A  
1B  
V
CC  
1
2
3
4
5
6
7
8
16  
15  
14  
13  
15  
14  
13  
12  
11  
10  
1B  
1CLR  
1Q  
2
3
4
5
6
7
1R /C  
1R /C  
ext ext  
ext ext  
1C  
1Q  
2Q  
3
2
1 20 19  
18  
ext  
1CLR  
1Q  
1C  
1Q  
ext  
1C  
1Q  
1CLR  
1Q  
4
5
6
7
8
ext  
17  
16  
2Q  
2Q  
12 2Q  
NC  
NC  
2C  
2CLR  
2B  
ext  
11  
10  
9
2C  
2CLR  
2B  
ext  
15 2Q  
2Q  
2R /C  
ext ext  
2R /C  
ext ext  
GND  
14  
9 10 11 12 13  
2CLR  
2C  
ext  
8
9
2A  
NC − No internal connection  
description/ordering information  
The ’LV123A devices are dual retriggerable monostable multivibrators designed for 2-V to 5.5-V V  
operation.  
CC  
These edge-triggered multivibrators feature output pulse-duration control by three methods. In the first method,  
the A input is low and the B input goes high. In the second method, the B input is high and the A input goes low.  
In the third method, the A input is low, the B input is high, and the clear (CLR) input goes high.  
The output pulse duration is programmable by selecting external resistance and capacitance values. The  
external timing capacitor must be connected between C  
and R /C  
(positive) and an external resistor  
ext  
ext ext  
connected between R /C  
resistance between R /C and V . The output pulse duration also can be reduced by taking CLR low.  
and V . To obtain variable pulse durations, connect an external variable  
ext ext  
CC  
ext ext  
CC  
Pulse triggering occurs at a particular voltage level and is not directly related to the transition time of the input  
pulse. The A, B, and CLR inputs have Schmitt triggers with sufficient hysteresis to handle slow input transition  
rates with jitter-free triggering at the outputs.  
Once triggered, the basic pulse duration can be extended by retriggering the gated low-level-active (A) or  
high-level-active (B) input. Pulse duration can be reduced by taking CLR low. The input/output timing diagram  
illustrates pulse control by retriggering the inputs and early clearing.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Copyright 2005, Texas Instruments Incorporated  
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1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567...23

中文翻译

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