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SN74LV123ADBR PDF预览

SN74LV123ADBR

更新时间： 2024-11-04 05:17:11
品牌 Logo 应用领域
德州仪器 - TI 预分频器多谐振动器触发器逻辑集成电路光电二极管输入元件时钟
页数 文件大小 规格书
23页 531K
描述
DUAL RETRIGGERABLE MONOSTABLE MULTIVIBRATORS WITH SCHMITT-TRIGGER INPUTS

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SN74LV123ADBR 技术参数

是否无铅：不含铅是否Rohs认证：符合
生命周期：Active零件包装代码：SOIC
包装说明：SSOP-16针数：16
Reach Compliance Code：compliantECCN代码：EAR99
HTS代码：8542.39.00.01Factory Lead Time：6 weeks
风险等级：1.31Is Samacsys：N
其他特性：EDGE TRIGGERED FROM ACTIVE-HIGH OR ACTIVE-LOW GATED LOGIC INPUTS系列：LV/LV-A/LVX/H
JESD-30 代码：R-PDSO-G16JESD-609代码：e4
长度：6.2 mm负载电容（CL）：50 pF
逻辑集成电路类型：MONOSTABLE MULTIVIBRATOR最大I（ol）：0.012 A
湿度敏感等级：1位数：2
数据/时钟输入次数：2功能数量：2
端子数量：16最高工作温度：125 °C
最低工作温度：-40 °C输出极性：COMPLEMENTARY
封装主体材料：PLASTIC/EPOXY封装代码：SSOP
封装等效代码：SSOP16,.3封装形状：RECTANGULAR
封装形式：SMALL OUTLINE, SHRINK PITCH包装方法：TR
峰值回流温度（摄氏度）：260电源：3.3 V
最大电源电流（ICC）：0.02 mA传播延迟（tpd）：42 ns
认证状态：Not Qualified施密特触发器：YES
座面最大高度：2 mm子类别：Prescaler/Multivibrators
最大供电电压 (Vsup)：5.5 V最小供电电压 (Vsup)：2 V
标称供电电压 (Vsup)：2.5 V表面贴装：YES
技术：CMOS温度等级：AUTOMOTIVE
端子面层：Nickel/Palladium/Gold (Ni/Pd/Au)端子形式：GULL WING
端子节距：0.65 mm端子位置：DUAL
处于峰值回流温度下的最长时间：NOT SPECIFIED宽度：5.3 mm
Base Number Matches：1

SN74LV123ADBR 数据手册

 浏览型号SN74LV123ADBR的Datasheet PDF文件第2页浏览型号SN74LV123ADBR的Datasheet PDF文件第3页浏览型号SN74LV123ADBR的Datasheet PDF文件第4页浏览型号SN74LV123ADBR的Datasheet PDF文件第5页浏览型号SN74LV123ADBR的Datasheet PDF文件第6页浏览型号SN74LV123ADBR的Datasheet PDF文件第7页 
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SCLS393O − APRIL 1998 − REVISED OCTOBER 2005  
D
D
D
D
D
D
D
2-V to 5.5-V V  
Operation  
D
D
D
D
D
I
Supports Partial-Power-Down Mode  
CC  
off  
Operation  
Max t of 11 ns at 5 V  
pd  
Retriggerable for Very Long Output Pulses,  
up to 100% Duty Cycle  
Typical V  
<0.8 V at V  
(Output Ground Bounce)  
OLP  
CC  
= 3.3 V, T = 25°C  
A
Overriding Clear Terminates Output Pulse  
Glitch-Free Power-Up Reset on Outputs  
Typical V  
>2.3 V at V  
(Output V  
Undershoot)  
OHV  
CC  
OH  
= 3.3 V, T = 25°C  
A
Support Mixed-Mode Voltage Operation on  
All Ports  
Latch-Up Performance Exceeds 100 mA Per  
JESD 78, Class II  
Schmitt-Trigger Circuitry on A, B, and CLR  
Inputs for Slow Input Transition Rates  
D
ESD Protection Exceeds JESD 22  
− 2000-V Human-Body Model (A114-A)  
− 200-V Machine Model (A115-A)  
Edge Triggered From Active-High or  
Active-Low Gated Logic Inputs  
− 1000-V Charged-Device Model (C101)  
SN74LV123A . . . RGY PACKAGE  
(TOP VIEW)  
SN54LV123A . . . FK PACKAGE  
(TOP VIEW)  
SN54LV123A . . . J OR W PACKAGE  
SN74LV123A . . . D, DB, DGV, NS,  
OR PW PACKAGE  
(TOP VIEW)  
1
16  
1A  
1B  
V
CC  
1
2
3
4
5
6
7
8
16  
15  
14  
13  
15  
14  
13  
12  
11  
10  
1B  
1CLR  
1Q  
2
3
4
5
6
7
1R /C  
1R /C  
ext ext  
ext ext  
1C  
1Q  
2Q  
3
2
1 20 19  
18  
ext  
1CLR  
1Q  
1C  
1Q  
ext  
1C  
1Q  
1CLR  
1Q  
4
5
6
7
8
ext  
17  
16  
2Q  
2Q  
12 2Q  
NC  
NC  
2C  
2CLR  
2B  
ext  
11  
10  
9
2C  
2CLR  
2B  
ext  
15 2Q  
2Q  
2R /C  
ext ext  
2R /C  
ext ext  
GND  
14  
9 10 11 12 13  
2CLR  
2C  
ext  
8
9
2A  
NC − No internal connection  
description/ordering information  
The ’LV123A devices are dual retriggerable monostable multivibrators designed for 2-V to 5.5-V V  
operation.  
CC  
These edge-triggered multivibrators feature output pulse-duration control by three methods. In the first method,  
the A input is low and the B input goes high. In the second method, the B input is high and the A input goes low.  
In the third method, the A input is low, the B input is high, and the clear (CLR) input goes high.  
The output pulse duration is programmable by selecting external resistance and capacitance values. The  
external timing capacitor must be connected between C  
and R /C  
(positive) and an external resistor  
ext  
ext ext  
connected between R /C  
resistance between R /C and V . The output pulse duration also can be reduced by taking CLR low.  
and V . To obtain variable pulse durations, connect an external variable  
ext ext  
CC  
ext ext  
CC  
Pulse triggering occurs at a particular voltage level and is not directly related to the transition time of the input  
pulse. The A, B, and CLR inputs have Schmitt triggers with sufficient hysteresis to handle slow input transition  
rates with jitter-free triggering at the outputs.  
Once triggered, the basic pulse duration can be extended by retriggering the gated low-level-active (A) or  
high-level-active (B) input. Pulse duration can be reduced by taking CLR low. The input/output timing diagram  
illustrates pulse control by retriggering the inputs and early clearing.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Copyright 2005, Texas Instruments Incorporated  
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1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567...23

中文翻译

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SN74LV123ADBR 替代型号

型号 品牌 替代类型 描述 数据表
SN74LV123ADBRG4 TI

完全替代

 DUAL RETRIGGERABLE MONOSTABLE MULTIVIBRATORS WITH SCHMITT-TRIGGER INPUTS
SN74LV123ADBRE4 TI

完全替代

 DUAL RETRIGGERABLE MONOSTABLE MULTIVIBRATORS WITH SCHMITT-TRIGGER INPUTS

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