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SN74LS323DW PDF预览

SN74LS323DW

更新时间: 2024-09-16 23:06:19
品牌 Logo 应用领域
摩托罗拉 - MOTOROLA 移位寄存器存储触发器逻辑集成电路光电二极管输出元件
页数 文件大小 规格书
5页 147K
描述
8-BIT SHIFT/STORAGE REGISTER WITH 3-STATE OUTPUTS

SN74LS323DW 技术参数

是否Rohs认证:不符合生命周期:Obsolete
包装说明:SOP, SOP20,.4Reach Compliance Code:unknown
HTS代码:8542.39.00.01风险等级:5.73
Is Samacsys:N其他特性:HOLD MODE; COMMON I/O PINS; TOTEMPOLE SERIAL SHIFT RIGHT & SHIFT LEFT OUTPUTS; GATED OUTPUT CONTROL
计数方向:BIDIRECTIONAL系列:LS
JESD-30 代码:R-PDSO-G20JESD-609代码:e0
长度:12.8 mm负载电容(CL):15 pF
逻辑集成电路类型:PARALLEL IN PARALLEL OUT最大频率@ Nom-Sup:25000000 Hz
位数:8功能数量:1
端子数量:20最高工作温度:70 °C
最低工作温度:输出特性:3-STATE
输出极性:TRUE封装主体材料:PLASTIC/EPOXY
封装代码:SOP封装等效代码:SOP20,.4
封装形状:RECTANGULAR封装形式:SMALL OUTLINE
峰值回流温度(摄氏度):NOT SPECIFIED电源:5 V
最大电源电流(ICC):53 mA传播延迟(tpd):39 ns
认证状态:Not Qualified座面最大高度:2.65 mm
子类别:Shift Registers最大供电电压 (Vsup):5.25 V
最小供电电压 (Vsup):4.75 V标称供电电压 (Vsup):5 V
表面贴装:YES技术:TTL
温度等级:COMMERCIAL端子面层:Tin/Lead (Sn/Pb)
端子形式:GULL WING端子节距:1.27 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
触发器类型:POSITIVE EDGE宽度:7.5 mm
最小 fmax:25 MHzBase Number Matches:1

SN74LS323DW 数据手册

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SN54/74LS323  
8-BIT SHIFT/STORAGE REGISTER  
WITH 3-STATE OUTPUTS  
The SN54/74LS323 is an 8-Bit Universal Shift/Storage Register with  
3-stateoutputs. ItsfunctionissimilartotheSN54/74LS299withtheexception  
of Synchronous Reset. Parallel load inputs and flip-flop outputs are  
multiplexed to minimize pin count. Separate inputs and outputs are provided  
8-BIT SHIFT/STORAGE REGISTER  
WITH 3-STATE OUTPUTS  
for flip-flops Q and Q to allow easy cascading.  
0
7
LOW POWER SCHOTTKY  
Four operation modes are possible: hold (store), shift left, shift right, and  
parallel load. All modes are activated on the LOW-to-HIGH transition of the  
Clock.  
Common I/O for Reduced Pin Count  
Four Operation Modes: Shift Left, Shift Right, Parallel Load and Store  
Separate Continuous Inputs and Outputs from Q and Q Allow Easy  
Cascading  
0
7
J SUFFIX  
CERAMIC  
CASE 732-03  
Fully Synchronous Reset  
3-State Outputs for Bus Oriented Applications  
Input Clamp Diodes Limit High-Speed Termination Effects  
ESD > 3500 Volts  
20  
1
N SUFFIX  
PLASTIC  
CASE 738-03  
20  
1
CONNECTION DIAGRAM DIP (TOP VIEW)  
V
S
DS  
Q
I/O  
I/O  
I/O  
I/O  
CP DS  
0
DW SUFFIX  
SOIC  
CASE 751D-03  
CC  
20  
1
7
7
7
5
3
1
19  
18  
17  
16  
15  
14  
13  
12  
11  
20  
1
NOTE:  
The Flatpak version  
has the same pinouts  
(Connection Diagram) as  
the Dual In-Line Package.  
ORDERING INFORMATION  
SN54LSXXXJ  
SN74LSXXXN Plastic  
SN74LSXXXDW SOIC  
Ceramic  
1
2
3
4
5
6
8
9
10  
7
S
0
OE OE  
I/O I/O  
I/O  
I/O  
Q
SR GND  
1
2
6
4
2
0
0
PIN NAMES  
LOADING (Note a)  
HIGH  
LOW  
CP  
Clock Pulse (active positive going edge) Input  
Serial Data Input for Right Shift  
Serial Data Input for Left Shift  
Parallel Data Input or  
Parallel Output (3-State) (Note c)  
3-State Output Enable (active LOW) Inputs  
Serial Outputs (Note b)  
0.5 U.L.  
0.5 U.L.  
0.5 U.L.  
1.0 U.L.  
0.25 U.L.  
0.25 U.L.  
0.25 U.L.  
0.5 U.L.  
DS  
DS  
0
7
n
I/O  
65 (25) U.L.  
15 (7.5) U.L.  
OE , OE  
0.5 U.L.  
10 U.L.  
1 U.L.  
0.25 U.L.  
5 (2.5) U.L.  
1
2
Q , Q  
0
7
1
S , S  
Mode Select Inputs  
0
SR  
Synchronous Reset (active LOW) Input  
0.5 U.L.  
0.25 U.L.  
NOTES:  
a) 1 TTL LOAD = 40 µA HIGH/1.6 mA LOW.  
b) The output LOW drive factor is 2.5 U.L for Military (54) and 5 U.L. for Commercial Temperature Ranges.  
c) The output LOW drive factor is 7.5 U.L for Military (54) and 15 U.L. for Commercial Temperature Ranges.  
The output HIGH drive factor is 25 U.L. for Military (54) and 65 U.L. for Commercial Temperature Ranges.  
FAST AND LS TTL DATA  
5-1  

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