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SN74LS323JDS PDF预览

SN74LS323JDS

更新时间: 2024-09-17 13:13:51
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摩托罗拉 - MOTOROLA 移位寄存器存储触发器逻辑集成电路光电二极管输出元件
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SN74LS323JDS 数据手册

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SN54/74LS323  
8-BIT SHIFT/STORAGE REGISTER  
WITH 3-STATE OUTPUTS  
The SN54/74LS323 is an 8-Bit Universal Shift/Storage Register with  
3-stateoutputs. ItsfunctionissimilartotheSN54/74LS299withtheexception  
of Synchronous Reset. Parallel load inputs and flip-flop outputs are  
multiplexed to minimize pin count. Separate inputs and outputs are provided  
8-BIT SHIFT/STORAGE REGISTER  
WITH 3-STATE OUTPUTS  
for flip-flops Q and Q to allow easy cascading.  
0
7
LOW POWER SCHOTTKY  
Four operation modes are possible: hold (store), shift left, shift right, and  
parallel load. All modes are activated on the LOW-to-HIGH transition of the  
Clock.  
Common I/O for Reduced Pin Count  
Four Operation Modes: Shift Left, Shift Right, Parallel Load and Store  
Separate Continuous Inputs and Outputs from Q and Q Allow Easy  
Cascading  
0
7
J SUFFIX  
CERAMIC  
CASE 732-03  
Fully Synchronous Reset  
3-State Outputs for Bus Oriented Applications  
Input Clamp Diodes Limit High-Speed Termination Effects  
ESD > 3500 Volts  
20  
1
N SUFFIX  
PLASTIC  
CASE 738-03  
20  
1
CONNECTION DIAGRAM DIP (TOP VIEW)  
V
S
DS  
Q
I/O  
I/O  
I/O  
I/O  
CP DS  
0
DW SUFFIX  
SOIC  
CASE 751D-03  
CC  
20  
1
7
7
7
5
3
1
19  
18  
17  
16  
15  
14  
13  
12  
11  
20  
1
NOTE:  
The Flatpak version  
has the same pinouts  
(Connection Diagram) as  
the Dual In-Line Package.  
ORDERING INFORMATION  
SN54LSXXXJ  
SN74LSXXXN Plastic  
SN74LSXXXDW SOIC  
Ceramic  
1
2
3
4
5
6
8
9
10  
7
S
0
OE OE  
I/O I/O  
I/O  
I/O  
Q
SR GND  
1
2
6
4
2
0
0
PIN NAMES  
LOADING (Note a)  
HIGH  
LOW  
CP  
Clock Pulse (active positive going edge) Input  
Serial Data Input for Right Shift  
Serial Data Input for Left Shift  
Parallel Data Input or  
Parallel Output (3-State) (Note c)  
3-State Output Enable (active LOW) Inputs  
Serial Outputs (Note b)  
0.5 U.L.  
0.5 U.L.  
0.5 U.L.  
1.0 U.L.  
0.25 U.L.  
0.25 U.L.  
0.25 U.L.  
0.5 U.L.  
DS  
DS  
0
7
n
I/O  
65 (25) U.L.  
15 (7.5) U.L.  
OE , OE  
0.5 U.L.  
10 U.L.  
1 U.L.  
0.25 U.L.  
5 (2.5) U.L.  
1
2
Q , Q  
0
7
1
S , S  
Mode Select Inputs  
0
SR  
Synchronous Reset (active LOW) Input  
0.5 U.L.  
0.25 U.L.  
NOTES:  
a) 1 TTL LOAD = 40 µA HIGH/1.6 mA LOW.  
b) The output LOW drive factor is 2.5 U.L for Military (54) and 5 U.L. for Commercial Temperature Ranges.  
c) The output LOW drive factor is 7.5 U.L for Military (54) and 15 U.L. for Commercial Temperature Ranges.  
The output HIGH drive factor is 25 U.L. for Military (54) and 65 U.L. for Commercial Temperature Ranges.  
FAST AND LS TTL DATA  
5-1  

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