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ꢌ ꢉꢍꢎ ꢏ ꢋꢐꢑꢐ ꢒꢒ ꢊꢒ ꢉꢒ ꢓ ꢐꢔ ꢀꢄ ꢎꢕ ꢏ ꢑꢊ ꢖ ꢎꢀ ꢏꢊ ꢑ
SCLS473A − APRIL 2003 − REVISED JANUARY 2004
D
Controlled Baseline
− One Assembly/Test Site, One Fabrication
Site
D
D
D
D
D
D
4-mA Output Drive at 5 V
Low Input Current of 1 µA Max
Complementary Outputs
D
D
Extended Temperature Performance of Up
To −55°C to 125°C
Enhanced Diminishing Manufacturing
Sources (DMS) Support
Direct Overriding Load (Data) Inputs
Gated Clock Inputs
Parallel-to-Serial Data Conversion
D
D
D
D
D
D
Enhanced Product-Change Notification
D OR PW PACKAGE
(TOP VIEW)
†
Qualification Pedigree
2-V to 6-V V
Operation
CC
SH/LD
CLK
E
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
V
CC
CLK INH
Outputs Can Drive Up To 10 LSTTL Loads
Low Power Consumption, 80-µA Max I
CC
D
C
B
A
Typical t = 13 ns
pd
F
G
H
†
Component qualification in accordance with JEDEC and industry
standards to ensure reliable operation over an extended
temperature range. This includes, but is not limited to, Highly
Accelerated Stress Test (HAST) or biased 85/85, temperature
cycle, autoclave or unbiased HAST, electromigration, bond
intermetallic life, and mold compound life. Such qualification
testing should not be viewed as justifying use of this component
beyond specified performance and environmental limits.
Q
SER
H
GND
Q
H
description/ordering information
The SN74HC165 is an 8-bit parallel-load shift register that, when clocked, shifts the data toward a serial (Q )
H
output. Parallel-in access to each stage is provided by eight individual direct data (A−H) inputs that are enabled
by a low level at the shift/load (SH/LD) input. The SN74HC165 device also features a clock-inhibit (CLK INH)
function and a complementary serial (Q ) output.
H
Clocking is accomplished by a low-to-high transition of the clock (CLK) input while SH/LD is held high and CLK
INH is held low. The functions of CLK and CLK INH are interchangeable. Since a low CLK and a low-to-high
transition of CLK INH also accomplish clocking, CLK INH should be changed to the high level only while CLK
is high. Parallel loading is inhibited when SH/LD is held high. While SH/LD is low, the parallel inputs to the
register are enabled independently of the levels of the CLK, CLK INH, or serial (SER) inputs.
ORDERING INFORMATION
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
‡
PACKAGE
T
A
SOIC − D
Tape and reel
Tape and reel
Tape and reel
SN74HC165QDREP
SN74HC165QPWREP
SN74HC165MDREP
HC165EP
−40°C to 125°C
−55°C to 125°C
TSSOP − PW
SOIC − D
HC165EP
HC165MEP
‡
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are
available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
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Copyright 2004, Texas Instruments Incorporated
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