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SN74F373N-10 PDF预览

SN74F373N-10

更新时间： 2024-02-04 15:15:38
品牌 Logo 应用领域
德州仪器 - TI 驱动光电二极管输出元件逻辑集成电路
页数 文件大小 规格书
16页 1018K
描述
F/FAST SERIES, 8-BIT DRIVER, TRUE OUTPUT, PDIP20

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SN74F373N-10 技术参数

生命周期：Obsolete包装说明：DIP,
Reach Compliance Code：unknownHTS代码：8542.39.00.01
风险等级：5.11系列：F/FAST
JESD-30 代码：R-PDIP-T20长度：24.325 mm
逻辑集成电路类型：BUS DRIVER位数：8
功能数量：1端口数量：2
端子数量：20最高工作温度：70 °C
最低工作温度：输出特性：3-STATE
输出极性：TRUE封装主体材料：PLASTIC/EPOXY
封装代码：DIP封装形状：RECTANGULAR
封装形式：IN-LINE传播延迟（tpd）：8 ns
认证状态：Not Qualified座面最大高度：5.08 mm
最大供电电压 (Vsup)：5.5 V最小供电电压 (Vsup)：4.5 V
标称供电电压 (Vsup)：5 V表面贴装：NO
技术：TTL温度等级：COMMERCIAL
端子形式：THROUGH-HOLE端子节距：2.54 mm
端子位置：DUAL宽度：7.62 mm
Base Number Matches：1

SN74F373N-10 数据手册

 浏览型号SN74F373N-10的Datasheet PDF文件第2页浏览型号SN74F373N-10的Datasheet PDF文件第3页浏览型号SN74F373N-10的Datasheet PDF文件第4页浏览型号SN74F373N-10的Datasheet PDF文件第5页浏览型号SN74F373N-10的Datasheet PDF文件第6页浏览型号SN74F373N-10的Datasheet PDF文件第7页 
SN54F373, SN74F373  
OCTAL TRANSPARENT D-TYPE LATCHES  
WITH 3-STATE OUTPUTS  
SDFS076A – D2932, MARCH 1987 – REVISED OCTOBER 1993  
SN54F373 . . . J PACKAGE  
SN74F373 . . . DB, DW, OR N PACKAGE  
(TOP VIEW)  
• Eight Latches in a Single Package  
• 3-State Bus-Driving True Outputs  
• Full Parallel Access for Loading  
• Buffered Control Inputs  
• Package Options Include Plastic  
Small-Outline (SOIC) and Shrink  
Small-Outline (SSOP) Packages, Ceramic  
Chip Carriers, and Plastic and Ceramic  
DIPs  
OE  
1Q  
1D  
2D  
2Q  
3Q  
3D  
4D  
4Q  
V
CC  
1
2
3
4
5
6
7
8
9
10  
20  
19  
18  
17  
16  
15  
14  
8Q  
8D  
7D  
7Q  
6Q  
6D  
13 5D  
12 5Q  
description  
These 8-bit latches feature 3-state outputs  
designed specifically for driving highly capacitive  
or relatively low-impedance loads. They are  
particularly suitable for implementing buffer  
registers, I/O ports, bidirectional bus drivers, and  
working registers.  
11  
GND  
LE  
SN54F373 . . . FK PACKAGE  
(TOP VIEW)  
The eight latches of the ′F373 are transparent  
D-type latches. While the latch-enable (LE) input  
ishigh, theQoutputswillfollowthedata(D)inputs.  
When the latch enable is taken low, the Q outputs  
are latched at the logic levels set up at the D  
inputs.  
3
2
1
20 19  
18  
2D  
2Q  
3Q  
3D  
4D  
4
5
6
7
8
8D  
7D  
7Q  
6Q  
6D  
17  
16  
15  
14  
9 10 11 12 13  
A buffered output-enable (OE) input can be used  
to place the eight outputs in either a normal  
logic state (high or low logic levels) or a  
high-impedance state. In the high-impedance  
state, the outputs neither load nor drive the bus  
lines significantly. The high-impedance state and  
increased drive provide the capability to drive bus  
lines without need for interface or pullup  
components.  
The output-enable (OE) input does not affect the internal operations of the latches. Old data can be retained  
or new data can be entered while the outputs are in the high-impedance state.  
The SN74F373 is available in TI’s shrink small-outline package (DB), which provides the same I/O pin count  
and functionality of standard small-outline packages in less than half the printed-circuit-board area.  
The SN54F373 is characterized for operation over the full military temperature range of –55°C to 125°C. The  
SN74F373 is characterized for operation from 0°C to 70°C.  
FUNCTION TABLE  
(each latch)  
INPUTS  
OUTPUT  
Q
OE  
L
LE  
H
H
L
D
H
L
H
L
L
L
X
X
Q
0
H
X
Z
Copyright 1993, Texas Instruments Incorporated  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567...16

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