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SN74BCT8373ADWE4

更新时间： 2024-11-03 22:53:35
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德州仪器 - TI 锁存器测试
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26页 469K
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SCAN TEST DEVICES WITH OCTAL D-TYPE LATCHES

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SN74BCT8373ADWE4 数据手册

 浏览型号SN74BCT8373ADWE4的Datasheet PDF文件第2页浏览型号SN74BCT8373ADWE4的Datasheet PDF文件第3页浏览型号SN74BCT8373ADWE4的Datasheet PDF文件第4页浏览型号SN74BCT8373ADWE4的Datasheet PDF文件第5页浏览型号SN74BCT8373ADWE4的Datasheet PDF文件第6页浏览型号SN74BCT8373ADWE4的Datasheet PDF文件第7页 
SN54BCT8373A, SN74BCT8373A  
SCAN TEST DEVICES  
WITH OCTAL D-TYPE LATCHES  
SCBS044F – JUNE 1990 – REVISED JULY 1996  
SN54BCT8373A . . . JT PACKAGE  
SN74BCT8373A . . . DW OR NT PACKAGE  
(TOP VIEW)  
Members of the Texas Instruments  
SCOPE Family of Testability Products  
Octal Test-Integrated Circuits  
LE  
1Q  
2Q  
3Q  
4Q  
GND  
5Q  
6Q  
OE  
1D  
2D  
3D  
4D  
5D  
V
1
2
3
4
5
6
7
8
9
24  
23  
22  
21  
20  
19  
18  
17  
16  
Functionally Equivalent to ’F373 and  
’BCT373 in the Normal-Function Mode  
Compatible With the IEEE Standard  
1149.1-1990 (JTAG) Test Access Port and  
Boundary-Scan Architecture  
Test Operation Synchronous to Test  
Access Port (TAP)  
CC  
6D  
7D  
Implement Optional Test Reset Signal by  
Recognizing a Double-High-Level Voltage  
(10 V) on TMS Pin  
7Q  
8Q 10  
15 8D  
TDO  
TMS  
TDI  
TCK  
11  
12  
14  
13  
SCOPE Instruction Set  
– IEEE Standard 1149.1-1990 Required  
Instructions, Optional INTEST, CLAMP,  
and HIGHZ  
– Parallel Signature Analysis at Inputs  
– Pseudo-Random Pattern Generation  
From Outputs  
SN54BCT8373A . . . FK PACKAGE  
(TOP VIEW)  
– Sample Inputs/Toggle Outputs  
4
3
2
1
28 27 26  
25  
5
6
7
8
9
2D  
1D  
OE  
NC  
LE  
8D  
TDI  
TCK  
Package Options Include Plastic  
Small-Outline (DW) Packages, Ceramic  
Chip Carriers (FK), and Standard Plastic  
and Ceramic 300-mil DIPs (JT, NT)  
24  
23  
22 NC  
21 TMS  
20 TDO  
19 8Q  
description  
10  
11  
1Q  
2Q  
The ’BCT8373A scan test devices with octal  
D-type latches are members of the Texas  
12 13 14 15 16 17 18  
Instruments SCOPE  
testability integrated-  
circuit family. This family of devices supports IEEE  
Standard 1149.1-1990 boundary scan to facilitate  
testing of complex circuit board assemblies. Scan  
access to the test circuitry is accomplished via the  
4-wire test access port (TAP) interface.  
NC – No internal connection  
In the normal mode, these devices are functionally equivalent to the ’F373 and ’BCT373 octal D-type latches.  
The test circuitry can be activated by the TAP to take snapshot samples of the data appearing at the device  
terminals or to perform a self test on the boundary test cells. Activating the TAP in normal mode does not affect  
the functional operation of the SCOPE octal latches.  
In the test mode, the normal operation of the SCOPE octal latches is inhibited and the test circuitry is enabled  
to observe and control the I/O boundary of the device. When enabled, the test circuitry can perform boundary  
scan test operations, as described in IEEE Standard 1149.1-1990.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
SCOPE is a trademark of Texas Instruments Incorporated.  
Copyright 1996, Texas Instruments Incorporated  
On products compliant to MIL-PRF-38535, all parameters are tested  
unless otherwise noted. On all other products, production  
processing does not necessarily include testing of all parameters.  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567...26

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SN74BCT8373ADWE4 替代型号

型号 品牌 替代类型 描述 数据表
SNJ54BCT8373AJT TI

完全替代

 SCAN TEST DEVICES WITH OCTAL D-TYPE LATCHES
SN74BCT8373ANT TI

完全替代

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SN74BCT8373ANTE4 TI

完全替代

 SCAN TEST DEVICES WITH OCTAL D-TYPE LATCHES

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