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SN74BCT8373NT PDF预览

SN74BCT8373NT

更新时间： 2024-11-04 13:02:47
品牌 Logo 应用领域
德州仪器 - TI 锁存器测试
页数 文件大小 规格书
21页 293K
描述
Scan Test Device With Octal D-Type Latches 24-PDIP 0 to 70

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中文翻译

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SN74BCT8373NT 技术参数

是否无铅：含铅是否Rohs认证：不符合
生命周期：Obsolete包装说明：DIP, DIP24,.3
Reach Compliance Code：not_compliantHTS代码：8542.39.00.01
Factory Lead Time：1 week风险等级：5.48
Is Samacsys：N系列：BCT/FBT
JESD-30 代码：R-PDIP-T24长度：31.64 mm
负载电容（CL）：50 pF逻辑集成电路类型：BOUNDARY SCAN BUS DRIVER
最大频率@ Nom-Sup：20000000 Hz最大I（ol）：0.064 A
位数：8功能数量：1
端口数量：2端子数量：24
最高工作温度：70 °C最低工作温度：
输出特性：3-STATE输出极性：TRUE
封装主体材料：PLASTIC/EPOXY封装代码：DIP
封装等效代码：DIP24,.3封装形状：RECTANGULAR
封装形式：IN-LINE峰值回流温度（摄氏度）：NOT SPECIFIED
电源：5 V最大电源电流（ICC）：52 mA
Prop。Delay @ Nom-Sup：10 ns传播延迟（tpd）：11.6 ns
认证状态：Not Qualified座面最大高度：5.08 mm
子类别：FF/Latches最大供电电压 (Vsup)：5.5 V
最小供电电压 (Vsup)：4.5 V标称供电电压 (Vsup)：5 V
表面贴装：NO技术：BICMOS
温度等级：COMMERCIAL端子形式：THROUGH-HOLE
端子节距：2.54 mm端子位置：DUAL
处于峰值回流温度下的最长时间：NOT SPECIFIED宽度：7.62 mm
Base Number Matches：1

SN74BCT8373NT 数据手册

 浏览型号SN74BCT8373NT的Datasheet PDF文件第2页浏览型号SN74BCT8373NT的Datasheet PDF文件第3页浏览型号SN74BCT8373NT的Datasheet PDF文件第4页浏览型号SN74BCT8373NT的Datasheet PDF文件第5页浏览型号SN74BCT8373NT的Datasheet PDF文件第6页浏览型号SN74BCT8373NT的Datasheet PDF文件第7页 
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SCBS471 − JUNE 1990 − REVISED JUNE 1994  
DW OR NT PACKAGE  
(TOP VIEW)  
• Member of the Texas Instruments SCOPE  
Family of Testability Products  
• Octal Test-Integrated Circuit  
LE  
1Q  
2Q  
3Q  
4Q  
GND  
5Q  
6Q  
OE  
1D  
2D  
3D  
4D  
5D  
V
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24  
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• Functionally Equivalent to SN74F373 and  
SN74BCT373 in the Normal-Function Mode  
• Compatible With the IEEE Standard  
1149.1-1990 (JTAG) Test Access Port and  
Boundary-Scan Architecture  
• Test Operation Synchronous to Test  
CC  
6D  
7D  
Access Port (TAP)  
7Q  
• Implements Optional Test Reset Signal by  
Recognizing a Double-High-Level Voltage  
(10 V) on TMS Pin  
8Q 10  
15 8D  
TDO  
TMS  
TDI  
TCK  
11  
12  
14  
13  
• SCOPE Instruction Set  
− IEEE Standard 1149.1-1990 Required  
Instructions, Optional INTEST, CLAMP  
and HIGHZ  
− Parallel-Signature Analysis at Inputs  
− Pseudo-Random Pattern Generation  
From Outputs  
− Sample Inputs/Toggle Outputs  
• Package Options Include Plastic  
Small-Outline (DW) Packages and  
Standard Plastic 300-mil DIPs (NT)  
description  
The SN74BCT8373 scan test device with octal D-type latches is a member of the Texas Instruments SCOPE  
testability integrated circuit family. This family of devices supports IEEE Standard 1149.1-1990 boundary scan  
to facilitate testing of complex circuit-board assemblies. Scan access to the test circuitry is accomplished via  
the 4-wire test access port (TAP) interface.  
In the normal mode, this device is functionally equivalent to the SN74F373 and SN74BCT373 octal D-type  
latches. The test circuitry can be activated by the TAP to take snapshot samples of the data appearing at the  
device terminals or to perform a self test on the boundary-test cells. Activating the TAP in normal mode does  
not affect the functional operation of the SCOPEoctal latches.  
In the test mode, the normal operation of the SCOPEoctal latches is inhibited and the test circuitry is enabled  
to observe and control the I/O boundary of the device. When enabled, the test circuitry can perform  
boundary-scan test operations as described in IEEE Standard 1149.1-1990.  
Four dedicated test terminals control the operation of the test circuitry: test data input (TDI), test data output  
(TDO), test mode select (TMS), and test clock (TCK). Additionally, the test circuitry performs other testing  
functions such as parallel-signature analysis (PSA) on data inputs and pseudo-random pattern generation  
(PRPG) from data outputs. All testing and scan operations are synchronized to the TAP interface.  
The SN74BCT8373 is characterized for operation from 0°C to 70°C.  
SCOPE is a trademark of Texas Instruments Incorporated.  
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Copyright 1994, Texas Instruments Incorporated  
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2−1  
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443  
1234567...21

中文翻译

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SN74BCT8373NT 替代型号

型号 品牌 替代类型 描述 数据表
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