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SCES540A − JANUARY 2004 − REVISED FEBRUARY 2004
DCT OR DCU PACKAGE
(TOP VIEW)
D
D
Available in the Texas Instruments
NanoStar and NanoFree Packages
Optimized for 1.8-V Operation and Is 3.6-V
I/O Tolerant to Support Mixed-Mode Signal
Operation
1
2
3
4
8
7
6
5
1CLK
1D
2Q
GND
V
CC
1Q
2D
2CLK
D
I
Supports Partial-Power-Down Mode
off
Operation
D
D
D
D
D
Sub 1-V Operable
YEP OR YZP PACKAGE
(BOTTOM VIEW)
Max t of 1.9 ns at 1.8 V
pd
Low Power Consumption, 10-µA Max I
CC
4 5
3 6
2 7
1 8
GND
2Q
1D
2CLK
2D
1Q
8-mA Output Drive at 1.8 V
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
1CLK
V
CC
D
ESD Protection Exceeds JESD 22
− 2000-V Human-Body Model (A114-A)
− 200-V Machine Model (A115-A)
− 1000-V Charged-Device Model (C101)
description/ordering information
This dual positive-edge-triggered D-type flip-flop is operational at 0.8-V to 2.7-V V , but is designed specifically
CC
for 1.65-V to 1.95-V V
operation.
CC
When data at the data (D) input meets the setup time requirement, the data is transferred to the Q output on
the positive-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not related directly
to the rise time of the clock pulse. Following the hold-time interval, data at the D input can be changed without
affecting the levels at the outputs.
NanoStar and NanoFree package technology is a major breakthrough in IC packaging concepts, using the
die as the package.
This device is fully specified for partial-power-down applications using I . The I circuitry disables the outputs,
off
off
preventing damaging current backflow through the device when it is powered down.
ORDERING INFORMATION
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
†
T
A
PACKAGE
‡
NanoStar − WCSP (DSBGA)
0.23-mm Large Bump − YEP
Tape and reel
Tape and reel
SN74AUC2G80YEPR
_ _ _UX_
NanoFree − WCSP (DSBGA)
0.23-mm Large Bump − YZP (Pb-free)
SN74AUC2G80YZPR
−40°C to 85°C
SSOP − DCT
Tape and reel
Tape and reel
SN74AUC2G80DCTR
SN74AUC2G80DCUR
U80_ _ _
UX_
VSSOP − DCU
†
‡
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available
at www.ti.com/sc/package.
DCT: The actual top-side marking has three additional characters that designate the year, month, and assembly/test site.
DCU: The actual top-side marking has one additional character that designates the assembly/test site.
YEP/YZP: The actual top-side marking has three preceding characters to denote year, month, and sequence code, and
one following character to designate the assembly/test site. Pin 1 identifier indicates solder-bump composition
(1 = SnPb, • = Pb-free).
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
NanoStar and NanoFree are trademarks of Texas Instruments.
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Copyright 2004, Texas Instruments Incorporated
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