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SN74ALVCH16260 PDF预览

SN74ALVCH16260

更新时间： 2024-11-17 23:09:43
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德州仪器 - TI 锁存器输出元件
页数 文件大小 规格书
10页 136K
描述
12-BIT TO 24-BIT MULTIPLEXED D-TYPE LATCH WITH 3-STATE OUTPUTS

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SN74ALVCH16260 数据手册

 浏览型号SN74ALVCH16260的Datasheet PDF文件第2页浏览型号SN74ALVCH16260的Datasheet PDF文件第3页浏览型号SN74ALVCH16260的Datasheet PDF文件第4页浏览型号SN74ALVCH16260的Datasheet PDF文件第5页浏览型号SN74ALVCH16260的Datasheet PDF文件第6页浏览型号SN74ALVCH16260的Datasheet PDF文件第7页 
SN74ALVCH16260  
12-BIT TO 24-BIT MULTIPLEXED D-TYPE LATCH  
WITH 3-STATE OUTPUTS  
SCES046E – JULY 1995 – REVISED FEBRUARY 1999  
DGG OR DL PACKAGE  
(TOP VIEW)  
Member of the Texas Instruments  
Widebus Family  
EPIC (Enhanced-Performance Implanted  
CMOS) Submicron Process  
OEA  
LE1B  
2B3  
GND  
2B2  
OE2B  
LEA2B  
2B4  
GND  
2B5  
1
56  
55  
54  
53  
52  
51  
50  
49  
48  
47  
46  
45  
44  
43  
42  
41  
40  
39  
38  
37  
36  
35  
34  
33  
32  
31  
30  
29  
2
ESD Protection Exceeds 2000 V Per  
MIL-STD-883, Method 3015; Exceeds 200 V  
Using Machine Model (C = 200 pF, R = 0)  
3
4
5
Latch-Up Performance Exceeds 250 mA Per  
JESD 17  
2B1  
2B6  
6
V
V
7
CC  
CC  
A1  
A2  
A3  
GND  
A4  
A5  
A6  
A7  
A8  
2B7  
2B8  
2B9  
8
Bus Hold on Data Inputs Eliminates the  
Need for External Pullup/Pulldown  
Resistors  
9
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
GND  
2B10  
2B11  
2B12  
1B12  
1B11  
1B10  
GND  
1B9  
Package Options Include Plastic Shrink  
Small-Outline (DL) and Thin Shrink  
Small-Outline (DGG) Packages  
description  
This 12-bit to 24-bit multiplexed D-type latch is  
designed for 1.65-V to 3.6-V operation.  
A9  
CC  
GND  
A10  
A11  
A12  
The SN74ALVCH16260 is used in applications in  
which two separate data paths must be  
multiplexed onto, or demultiplexed from, a single  
data path. Typical applications include  
multiplexing and/or demultiplexing address and  
1B8  
1B7  
V
V
CC  
CC  
1B1  
1B2  
GND  
1B3  
LE2B  
SEL  
1B6  
1B5  
GND  
1B4  
LEA1B  
OE1B  
data  
information  
in  
microprocessor  
or  
bus-interface applications. This device also is  
useful in memory-interleaving applications.  
Three 12-bit I/O ports (A1–A12, 1B1–1B12, and  
2B1–2B12) are available for address and/or data  
transfer. The output-enable (OE1B, OE2B, and  
OEA) inputs control the bus transceiver functions.  
The OE1B and OE2B control signals also allow  
bank control in the A-to-B direction.  
Address and/or data information can be stored using the internal storage latches. The latch-enable (LE1B,  
LE2B, LEA1B, and LEA2B) inputs are used to control data storage. When the latch-enable input is high, the  
latch is transparent. When the latch-enable input goes low, the data present at the inputs is latched and remains  
latched until the latch-enable input is returned high.  
To ensure the high-impedance state during power up or power down, OE should be tied to V through a pullup  
CC  
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.  
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.  
The SN74ALVCH16260 is characterized for operation from –40°C to 85°C.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
EPIC and Widebus are trademarks of Texas Instruments Incorporated.  
Copyright 1999, Texas Instruments Incorporated  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567...10

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SN74ALVCH16260 替代型号

型号 品牌 替代类型 描述 数据表
SN74ALVC16260 TI

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