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SN74ALVCH16269KR

更新时间： 2024-11-18 05:29:35
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德州仪器 - TI 输出元件
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16页 442K
描述
12-BIT TO 24-BIT REGISTERED BUS EXCHANGER WITH 3-STATE OUTPUTS

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SN74ALVCH16269KR 数据手册

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SN74ALVCH16269  
12-BIT TO 24-BIT REGISTERED BUS EXCHANGER  
WITH 3-STATE OUTPUTS  
www.ti.com  
SCES019N–JULY 1995–REVISED JULY 2004  
FEATURES  
DGG OR DL PACKAGE  
(TOP VIEW)  
•
Member of the Texas Instruments Widebus™  
Family  
1
56  
55  
54  
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40  
39  
38  
37  
36  
35  
34  
33  
32  
31  
30  
29  
OEA  
OEB1  
2B3  
GND  
2B2  
•
•
•
•
Operates From 1.65 V to 3.6 V  
Max tpd of 5 ns at 3.3 V  
OEB2  
CLKENA2  
2B4  
GND  
2B5  
2
3
±24-mA Output Drive at 3.3 V  
4
Bus Hold on Data Inputs Eliminates the Need  
for External Pullup/Pulldown Resistors  
5
6
2B1  
2B6  
•
•
Latch-Up Performance Exceeds 250 mA Per  
JESD 17  
7
V
CC  
V
CC  
8
A1  
A2  
A3  
GND  
A4  
A5  
2B7  
2B8  
2B9  
9
ESD Protection Exceeds JESD 22  
– 2000-V Human-Body Model (A114-A)  
– 200-V Machine Model (A115-A)  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
GND  
2B10  
2B11  
2B12  
1B12  
1B11  
1B10  
GND  
1B9  
DESCRIPTION/ORDERING INFORMATION  
A6  
A7  
A8  
A9  
GND  
A10  
A11  
A12  
This 12-bit to 24-bit registered bus exchanger is  
designed for 1.65-V to 3.6-V VCC operation.  
The SN74ALVCH16269 is used in applications in  
which two separate ports must be multiplexed onto,  
or demultiplexed from, a single port. The device is  
particularly suitable as an interface between  
synchronous  
microprocessors.  
1B8  
1B7  
DRAMs  
and  
high-speed  
V
CC  
V
CC  
Data is stored in the internal B-port registers on the  
low-to-high transition of the clock (CLK) input when  
the appropriate clock-enable (CLKENA) inputs are  
low. Proper control of these inputs allows two  
sequential 12-bit words to be presented as a 24-bit  
word on the B port. For data transfer in the B-to-A  
direction, a single storage register is provided. The  
select (SEL) line selects 1B or 2B data for the A  
outputs. The register on the A output permits the  
fastest possible data transfer, extending the period  
during which the data is valid on the bus. The control  
terminals are registered so that all transactions are  
synchronous with CLK. Data flow is controlled by the  
active-low output enables (OEA, OEB1, OEB2).  
1B1  
1B2  
GND  
1B3  
NC  
1B6  
1B5  
GND  
1B4  
CLKENA1  
CLK  
SEL  
NC − No internal connection  
ORDERING INFORMATION  
TA  
PACKAGE(1)  
ORDERABLE PART NUMBER  
SN74ALVCH16269DL  
TOP-SIDE MARKING  
ALVCH16269  
ALVCH16269  
VH269  
Tube  
SSOP - DL  
Tape and reel  
Tape and reel  
SN74ALVCH16269DLR  
SN74ALVCH16269DGGR  
SN74ALVCH16269KR  
-40°C to 85°C  
TSSOP - DGG  
VFBGA - GQL  
Tape and reel  
VFBGA - ZQL (Pb-free)  
74ALVCH16269ZQLR  
(1) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at  
www.ti.com/sc/package.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas  
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Widebus is a trademark of Texas Instruments.  
PRODUCTION DATA information is current as of publication date.  
Copyright © 1995–2004, Texas Instruments Incorporated  
Products conform to specifications per the terms of the Texas  
Instruments standard warranty. Production processing does not  
necessarily include testing of all parameters.  
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