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SN74ALVCH16271DLR

更新时间： 2024-09-15 05:29:35
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德州仪器 - TI 输出元件
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15页 222K
描述
12-BIT TO 24-BIT MULTIPLEXED BUS EXCHANGER WITH 3-STATE OUTPUTS

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SN74ALVCH16271DLR 数据手册

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SN74ALVCH16271  
12-BIT TO 24-BIT MULTIPLEXED BUS EXCHANGER  
WITH 3-STATE OUTPUTS  
www.ti.com  
SCES017G–JULY 1995–REVISED SEPTEMBER 2004  
FEATURES  
DGG OR DL PACKAGE  
(TOP VIEW)  
•
•
•
•
Member of the Texas Instruments Widebus™  
Family  
OEA  
LE1B  
2B3  
1
2
3
4
5
6
7
8
9
10  
56  
55  
54  
53  
52  
51  
50  
49  
48  
47  
46  
45  
44  
43  
42  
41  
40  
39  
38  
37  
36  
35  
34  
33  
32  
31  
30  
29  
OEB  
CLKENA2  
2B4  
Bus Hold on Data Inputs Eliminates the Need  
for External Pullup/Pulldown Resistors  
Latch-Up Performance Exceeds 250 mA Per  
JESD 17  
GND  
2B2  
GND  
2B5  
ESD Protection Exceeds JESD 22  
- 2000-V Human-Body Model (A114-A)  
- 200-V Machine Model (A115-A)  
2B1  
2B6  
V
CC  
V
CC  
A1  
A2  
A3  
2B7  
2B8  
2B9  
DESCRIPTION/ORDERING INFORMATION  
This 12-bit to 24-bit bus exchanger is designed for  
1.65-V to 3.6-V VCC operation.  
GND 11  
A4 12  
A5 13  
GND  
2B10  
2B11  
2B12  
1B12  
1B11  
1B10  
GND  
1B9  
The SN74ALVCH16271 is intended for applications in  
which two separate data paths must be multiplexed  
onto, or demultiplexed from, a single data path. This  
device is particularly suitable as an interface  
between conventional DRAMs and high-speed  
microprocessors.  
14  
15  
16  
17  
A6  
A7  
A8  
A9  
GND 18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
A data is stored in the internal A-to-B registers on the  
low-to-high transition of the clock (CLK) input,  
provided that the clock-enable (CLKENA) inputs are  
low. Proper control of these inputs allows two  
sequential 12-bit words to be presented as a 24-bit  
word on the B port.  
A10  
A11  
A12  
1B8  
1B7  
V
CC  
V
CC  
1B1  
1B2  
1B6  
1B5  
Transparent latches in the B-to-A path allow  
asynchronous operation to maximize memory access  
throughput. These latches transfer data when the  
latch-enable (LE) inputs are low. The select (SEL)  
line selects 1B or 2B data for the A outputs. Data flow  
is controlled by the active-low output enables (OEA,  
OEB).  
GND  
1B3  
LE2B  
SEL  
GND  
1B4  
CLKENA1  
CLK  
line  
space  
To ensure the high-impedance state during power up or power down, the output enables should be tied to VCC  
through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the  
driver.  
Active bus-hold circuitry holds unused or undriven inputs at a valid logic state. Use of pullup or pulldown resistors  
with the bus-hold circuitry is not recommended.  
ORDERING INFORMATION  
ORDERABLE  
PART NUMBER  
TOP-SIDE  
MARKING  
TA  
PACKAGE(1)  
Tube  
SN74ALVCH16271DL  
SN74ALVCH16271DLR  
SSOP - DL  
TSSOP - DGG  
ALVCH16271  
-40°C to 85°C  
Tape and reel  
Tape and reel  
SN74ALVCH16271DGGR ALVCH16271  
(1) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design  
guidelines are available at www.ti.com/sc/package.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas  
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Widebus is a trademark of Texas Instruments.  
PRODUCTION DATA information is current as of publication date.  
Copyright © 1995–2004, Texas Instruments Incorporated  
Products conform to specifications per the terms of the Texas  
Instruments standard warranty. Production processing does not  
necessarily include testing of all parameters.  
1234567...15

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