SN74ALVCH162721
3.3-V 20-BIT FLIP-FLOP
WITH 3-STATE OUTPUTS
SCES055E – DECEMBER 1995 – REVISED JUNE 1999
DGG OR DL PACKAGE
(TOP VIEW)
Member of the Texas Instruments
Widebus Family
EPIC (Enhanced-Performance Implanted
CMOS) Submicron Process
OE
Q1
Q2
GND
Q3
Q4
1
2
3
4
5
6
7
8
9
56 CLK
55 D1
54 D2
53 GND
52 D3
51 D4
Output Ports Have Equivalent 26-Ω Series
Resistors, So No External Resistors Are
Required
ESD Protection Exceeds 2000 V Per
MIL-STD-883, Method 3015; Exceeds 200 V
Using Machine Model (C = 200 pF, R = 0)
V
50
V
CC
CC
Q5
Q6
Q7 10
GND 11
Q8 12
49 D5
48 D6
47 D7
46 GND
45 D8
44 D9
43 D10
Latch-Up Performance Exceeds 250 mA Per
JESD 17
Bus Hold on Data Inputs Eliminates the
Need for External Pullup/Pulldown
Resistors
Q9 13
Q10 14
Package Options Include Plastic 300-mil
Shrink Small-Outline (DL) and Thin Shrink
Small-Outline (DGG) Packages
NOTE: For tape and reel order entry:
15
42
Q11
Q12 16
Q13 17
D11
41 D12
40 D13
The DGGR package is abbreviated to GR.
18
19
20
21
22
23
24
25
26
27
28
39
38
37
36
35
34
33
32
31
30
29
GND
Q14
Q15
Q16
GND
D14
D15
D16
description
This 20-bit flip-flop is designed for low-voltage
V
V
CC
CC
1.65-V to 3.6-V V
operation.
CC
Q17
Q18
GND
Q19
Q20
NC
D17
D18
GND
D19
D20
The 20 flip-flops of the SN74ALVCH162721 are
edge-triggered D-type flip-flops with qualified
clock storage. On the positive transition of the
clock (CLK) input, the device provides true data at
the Q outputs if the clock-enable (CLKEN) input is
low. If CLKEN is high, no data is stored.
CLKEN
A buffered output-enable (OE) input places the 20
outputs in either a normal logic state (high or low
level) or the high-impedance state. In the
high-impedance state, the outputs neither load
NC – No internal connection
nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive
bus lines without interface or pullup components. OE does not affect the internal operation of the flip-flops. Old
data can be retained or new data can be entered while the outputs are in the high-impedance state.
To ensure the high-impedance state during power up or power down, OE should be tied to V through a pullup
CC
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.
The outputs, which are designed to sink up to 12 mA, include equivalent 26-Ω resistors to reduce overshoot and
undershoot.
The SN74ALVCH162721 is characterized for operation from –40°C to 85°C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC and Widebus are trademarks of Texas Instruments Incorporated.
Copyright 1999, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
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