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SN74ALVCH16271DGG

更新时间： 2024-09-14 23:09:43
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德州仪器 - TI 输出元件
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10页 139K
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12-BIT TO 24-BIT MULTIPLEXED BUS EXCHANGER WITH 3-STATE OUTPUTS

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SN74ALVCH16271DGG 数据手册

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SN74ALVCH16271  
12-BIT TO 24-BIT MULTIPLEXED BUS EXCHANGER  
WITH 3-STATE OUTPUTS  
SCES017E – JULY 1995 – REVISED FEBRUARY 1999  
DGG OR DL PACKAGE  
(TOP VIEW)  
Member of the Texas Instruments  
Widebus Family  
EPIC (Enhanced-Performance Implanted  
CMOS) Submicron Process  
OEA  
LE1B  
2B3  
GND  
2B2  
1
56  
55  
54  
53  
52  
51  
50  
49  
48  
47  
46  
45  
44  
43  
42  
41  
40  
39  
38  
37  
36  
35  
34  
33  
32  
31  
30  
29  
OEB  
CLKENA2  
2B4  
GND  
2B5  
2B6  
2
ESD Protection Exceeds 2000 V Per  
MIL-STD-883, Method 3015; Exceeds 200 V  
Using Machine Model (C = 200 pF, R = 0)  
3
4
5
Latch-Up Performance Exceeds 250 mA Per  
JESD 17  
2B1  
6
V
7
V
CC  
CC  
A1  
A2  
A3  
GND  
A4  
8
Bus Hold on Data Inputs Eliminates the  
Need for External Pullup/Pulldown  
Resistors  
2B7  
2B8  
2B9  
9
10  
11  
12  
GND  
2B10  
2B11  
2B12  
1B12  
1B11  
1B10  
GND  
1B9  
Package Options Include Plastic Shrink  
Small-Outline (DL) and Thin Shrink  
Small-Outline (DGG) Packages  
A5 13  
A6 14  
A7 15  
description  
A8 16  
This 12-bit to 24-bit bus exchanger is designed for  
1.65-V to 3.6-V V operation.  
A9 17  
CC  
GND 18  
A10 19  
A11 20  
A12 21  
The SN74ALVCH16271 is intended for  
applications in which two separate data paths  
must be multiplexed onto, or demultiplexed from,  
a single data path. This device is particularly  
suitable as an interface between conventional  
DRAMs and high-speed microprocessors.  
1B8  
1B7  
V
22  
V
CC  
CC  
1B1 23  
1B2 24  
GND 25  
1B3 26  
LE2B 27  
SEL 28  
1B6  
1B5  
GND  
1B4  
CLKENA1  
CLK  
A data is stored in the internal A-to-B registers on  
the low-to-high transition of the clock (CLK) input,  
provided that the clock-enable (CLKENA) inputs  
are low. Proper control of these inputs allows two  
sequential 12-bit words to be presented as a  
24-bit word on the B port.  
Transparent latches in the B-to-A path allow asynchronous operation to maximize memory access throughput.  
These latches transfer data when the latch-enable (LE) inputs are low. The select (SEL) line selects 1B or 2B  
data for the A outputs. Data flow is controlled by the active-low output enables (OEA, OEB).  
To ensure the high-impedance state during power up or power down, the output enables should be tied to V  
CC  
through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of  
the driver.  
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.  
The SN74ALVCH16271 is characterized for operation from –40°C to 85°C.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
EPIC and Widebus are trademarks of Texas Instruments Incorporated.  
Copyright 1999, Texas Instruments Incorporated  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567...10

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SN74ALVCH162721DLR TI

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