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SN74ALVCH16270_08

更新时间： 2024-09-15 02:58:39
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德州仪器 - TI 输出元件
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10页 140K
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12-BIT TO 24-BIT REGISTERED BUS EXCHANGER WITH 3-STATE OUTPUTS

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SN74ALVCH16270_08 数据手册

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SN74ALVCH16270  
12-BIT TO 24-BIT REGISTERED BUS EXCHANGER  
WITH 3-STATE OUTPUTS  
SCES028F – JULY 1995 – REVISED FEBRUARY 1999  
DGG OR DL PACKAGE  
(TOP VIEW)  
Member of the Texas Instruments  
Widebus Family  
EPIC (Enhanced-Performance Implanted  
CMOS) Submicron Process  
OEA  
CLKEN1B  
2B3  
1
56  
55  
54  
53  
52  
51  
50  
49  
48  
47  
46  
45  
44  
43  
42  
41  
40  
39  
38  
37  
36  
35  
34  
33  
32  
31  
30  
29  
OEB  
CLKENA2  
2B4  
GND  
2B5  
2B6  
2
Bus Hold on Data Inputs Eliminates the  
Need for External Pullup/Pulldown  
Resistors  
3
GND  
2B2  
2B1  
4
5
ESD Protection Exceeds 2000 V Per  
MIL-STD-883, Method 3015; Exceeds 200 V  
Using Machine Model (C = 200 pF, R = 0)  
6
V
7
V
CC  
CC  
A1  
A2  
A3  
GND  
A4  
8
2B7  
2B8  
2B9  
Latch-Up Performance Exceeds 250 mA Per  
JESD 17  
9
10  
11  
12  
GND  
2B10  
2B11  
2B12  
1B12  
1B11  
1B10  
GND  
1B9  
Package Options Include Plastic Shrink  
Small-Outline (DL) and Thin Shrink  
Small-Outline (DGG) Packages  
A5 13  
A6 14  
A7 15  
description  
A8 16  
This 12-bit to 24-bit registered bus exchanger is  
designed for 1.65-V to 3.6-V V operation.  
A9 17  
CC  
GND 18  
A10 19  
A11 20  
A12 21  
The SN74ALVCH16270 is used in applications in  
which data must be transferred from a narrow  
high-speed bus to a wide lower-frequency bus.  
1B8  
1B7  
V
22  
V
CC  
CC  
The device provides synchronous data exchange  
between the two ports. Data is stored in the  
internal registers on the low-to-high transition of  
the clock (CLK) input when the appropriate  
CLKEN inputs are low. The select (SEL) line  
selects 1B or 2B data for the A outputs. For data  
transfer in the A-to-B direction, a two-stage  
pipeline is provided in the A-to-1B path, with a  
single storage register in the A-to-2B path.  
1B1 23  
1B2 24  
1B6  
1B5  
GND  
1B4  
CLKENA1  
CLK  
GND 25  
1B3 26  
CLKEN2B 27  
SEL 28  
Proper control of the CLKENA inputs allows two sequential 12-bit words to be presented synchronously as a  
24-bit word on the B port. Data flow is controlled by the active-low output enables (OEA, OEB). The control  
terminals are registered to synchronize the bus-direction changes with CLK.  
To ensure the high-impedance state during power up or power down, a clock pulse should be applied as soon  
as possible and OE should be tied to V  
through a pullup resistor; the minimum value of the resistor is  
CC  
determined by the current-sinking capability of the driver. Due to OE being routed through a register, the active  
state of the outputs cannot be determined prior to the arrival of the first clock pulse.  
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.  
The SN74ALVCH16270 is characterized for operation from –40°C to 85°C.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
EPIC and Widebus are trademarks of Texas Instruments Incorporated.  
Copyright 1999, Texas Instruments Incorporated  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567...10

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