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SN74ALVCH16269DGG

更新时间： 2024-11-17 23:09:43
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德州仪器 - TI 输出元件
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10页 142K
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12-BIT TO 24-BIT REGISTERED BUS EXCHANGER WITH 3-STATE OUTPUTS

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SN74ALVCH16269DGG 数据手册

 浏览型号SN74ALVCH16269DGG的Datasheet PDF文件第2页浏览型号SN74ALVCH16269DGG的Datasheet PDF文件第3页浏览型号SN74ALVCH16269DGG的Datasheet PDF文件第4页浏览型号SN74ALVCH16269DGG的Datasheet PDF文件第5页浏览型号SN74ALVCH16269DGG的Datasheet PDF文件第6页浏览型号SN74ALVCH16269DGG的Datasheet PDF文件第7页 
SN74ALVCH16269  
12-BIT TO 24-BIT REGISTERED BUS EXCHANGER  
WITH 3-STATE OUTPUTS  
SCES019I – JULY 1995 – REVISED SEPTEMBER 1999  
DGG OR DL PACKAGE  
(TOP VIEW)  
Member of the Texas Instruments  
Widebus Family  
EPIC (Enhanced-Performance Implanted  
CMOS) Submicron Process  
OEA  
OEB1  
2B3  
GND  
2B2  
1
56  
55  
54  
53  
52  
51  
50  
49  
48  
47  
46  
45  
44  
43  
42  
41  
40  
39  
38  
37  
36  
35  
34  
33  
32  
31  
30  
29  
OEB2  
CLKENA2  
2B4  
GND  
2B5  
2
ESD Protection Exceeds 2000 V Per  
MIL-STD-883, Method 3015; Exceeds 200 V  
Using Machine Model (C = 200 pF, R = 0)  
3
4
5
Latch-Up Performance Exceeds 250 mA Per  
JESD 17  
2B1  
6
2B6  
V
7
V
CC  
CC  
A1  
A2  
A3  
GND  
A4  
A5  
A6  
A7  
A8  
8
Bus Hold on Data Inputs Eliminates the  
Need for External Pullup/Pulldown  
Resistors  
2B7  
2B8  
2B9  
9
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
GND  
2B10  
2B11  
2B12  
1B12  
1B11  
1B10  
GND  
1B9  
Package Options Include Plastic Shrink  
Small-Outline (DL) and Thin Shrink  
Small-Outline (DGG) Packages  
description  
This 12-bit to 24-bit registered bus exchanger is  
designed for 1.65-V to 3.6-V V operation.  
A9  
CC  
GND  
A10  
A11  
A12  
The SN74ALVCH16269 is used in applications in  
which two separate ports must be multiplexed  
onto, or demultiplexed from, a single port. The  
device is particularly suitable as an interface  
between synchronous DRAMs and high-speed  
microprocessors.  
1B8  
1B7  
V
V
CC  
CC  
1B1  
1B2  
GND  
1B3  
NC  
1B6  
1B5  
GND  
1B4  
CLKENA1  
CLK  
Data is stored in the internal B-port registers on  
the low-to-high transition of the clock (CLK) input  
when the appropriate clock-enable (CLKENA)  
inputs are low. Proper control of these inputs  
allows two sequential 12-bit words to be  
presented as a 24-bit word on the B port. For data  
transfer in the B-to-A direction, a single storage  
SEL  
NC – No internal connection  
register is provided. The select (SEL) line selects 1B or 2B data for the A outputs. The register on the A output  
permits the fastest possible data transfer, extending the period during which the data is valid on the bus. The  
control terminals are registered so that all transactions are synchronous with CLK. Data flow is controlled by  
the active-low output enables (OEA, OEB1, OEB2).  
To ensure the high-impedance state during power up or power down, a clock pulse should be applied as soon  
as possible, and OE should be tied to V  
through a pullup resistor; the minimum value of the resistor is  
CC  
determined by the current-sinking capability of the driver. Due to OE being routed through a register, the active  
state of the outputs cannot be determined before the arrival of the first clock pulse.  
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.  
The SN74ALVCH16269 is characterized for operation from –40°C to 85°C.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
EPIC and Widebus are trademarks of Texas Instruments Incorporated.  
Copyright 1999, Texas Instruments Incorporated  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567...10

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