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SN74ALVC16373DLR

更新时间： 2024-11-09 13:13:47
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德州仪器 - TI 锁存器输出元件
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SN74ALVC16373DLR 数据手册

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SN74ALVC16373  
16-BIT TRANSPARENT D-TYPE LATCH  
WITH 3-STATE OUTPUTS  
SCAS257B – JANUARY 1993 – REVISED JULY 1995  
DGG OR DL PACKAGE  
(TOP VIEW)  
Member of the Texas Instruments  
Widebus Family  
EPIC (Enhanced-Performance Implanted  
CMOS) Submicron Process  
1
48  
47  
46  
45  
44  
43  
42  
41  
40  
39  
38  
37  
36  
35  
34  
33  
32  
31  
30  
29  
28  
27  
26  
25  
1OE  
1Q1  
1Q2  
GND  
1Q3  
1Q4  
1LE  
1D1  
1D2  
GND  
1D3  
1D4  
2
Typical V  
< 0.8 V at V  
(Output Ground Bounce)  
OLP  
3
= 3.3 V, T = 25°C  
CC  
A
4
Typical V  
> 2 V at V  
(Output V  
Undershoot)  
OHV  
CC  
OH  
5
= 3.3 V, T = 25°C  
A
6
Bus Hold on Data Inputs Eliminates the  
Need for External Pullup/Pulldown  
Resistors  
7
V
V
CC  
CC  
8
1Q5  
1Q6  
GND  
1Q7  
1Q8  
2Q1  
2Q2  
GND  
2Q3  
2Q4  
1D5  
1D6  
GND  
1D7  
1D8  
2D1  
2D2  
GND  
2D3  
2D4  
9
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
ESD Protection Exceeds 2000 V Per  
MIL-STD-833C, Method 3015; Exceeds  
200 V Using Machine Model  
(C = 200 pF, R = 0)  
Latch-Up Performance Exceeds 250 mA  
Per JEDEC Standard JESD-17  
Package Options Include Plastic 300-mil  
Shrink Small-Outline (DL) and Thin Shrink  
Small-Outline (DGG) Packages  
V
V
CC  
CC  
2Q5  
2Q6  
GND  
2Q7  
2Q8  
2OE  
2D5  
2D6  
GND  
2D7  
2D8  
2LE  
description  
This 16-bit transparent D-type latch is designed  
for 3.3-V V operation; it is tested at 2.5-V, 2.7-V,  
CC  
CC  
and 3.3-V V  
.
The SN74ALVC16373 is particularly suitable  
for implementing buffer registers, I/O ports,  
bidirectional bus drivers, and working registers. This device can be used as two 8-bit latches or one 16-bit latch.  
When the latch-enable (LE) input is high, the Q outputs follow the data (D) inputs. When LE is taken low, the  
Q outputs are latched at the levels set up at the D inputs.  
A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high-  
or low-logic levels) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive  
the bus lines significantly. The high-impedance state and the increased drive provide the capability to drive bus  
lines without need for interface or pullup components. OE does not affect internal operations of the latch. Old  
data can be retained or new data can be entered while the outputs are in the high-impedance state.  
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.  
The SN74ALVC16373 is available in TI’s shrink small-outline (DL) and thin shrink small-outline (DGG)  
packages, which provide twice the I/O pin count and functionality of standard small-outline packages in the  
same printed-circuit-board area.  
The SN74ALVC16373 is characterized for operation from –40°C to 85°C.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
EPIC and Widebus are trademarks of Texas Instruments Incorporated.  
Copyright 1995, Texas Instruments Incorporated  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
12345678

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