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SN74ALVC16501DGG

更新时间： 2024-11-06 13:13:47
品牌 Logo 应用领域
德州仪器 - TI 总线收发器输出元件
页数 文件大小 规格书
11页 196K
描述
ALVC/VCX/A SERIES, 18-BIT REGISTERED TRANSCEIVER, TRUE OUTPUT, PDSO56, 0.300 INCH, PLASTIC, TSSOP-56

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SN74ALVC16501DGG 技术参数

生命周期：Obsolete零件包装代码：TSSOP
包装说明：0.300 INCH, PLASTIC, TSSOP-56针数：56
Reach Compliance Code：unknown风险等级：5.5
Is Samacsys：N其他特性：WITH INDEPENDENT OUTPUT ENABLE FOR EACH DIRECTION
系列：ALVC/VCX/AJESD-30 代码：R-PDSO-G56
长度：14 mm逻辑集成电路类型：REGISTERED BUS TRANSCEIVER
位数：18功能数量：1
端口数量：2端子数量：56
最高工作温度：85 °C最低工作温度：-40 °C
输出特性：3-STATE输出极性：TRUE
封装主体材料：PLASTIC/EPOXY封装代码：TSSOP
封装形状：RECTANGULAR封装形式：SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
传播延迟（tpd）：6.7 ns认证状态：Not Qualified
座面最大高度：1.2 mm最大供电电压 (Vsup)：3.6 V
最小供电电压 (Vsup)：2.3 V标称供电电压 (Vsup)：2.5 V
表面贴装：YES技术：CMOS
温度等级：INDUSTRIAL端子形式：GULL WING
端子节距：0.5 mm端子位置：DUAL
宽度：6.1 mmBase Number Matches：1

SN74ALVC16501DGG 数据手册

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SCAS261A − JANUARY 1993 − REVISED JULY 1995  
DGG OR DL PACKAGE  
(TOP VIEW)  
D EPIC (Enhanced-Performance Implanted  
CMOS) Submicron Process  
D Member of the Texas Instruments  
D UBT (Universal Bus Transceiver)  
Combines D-Type Latches and D-Type  
Flip-Flops for Operation in Transparent,  
Latched, or Clocked Mode  
OEAB  
LEAB  
A1  
GND  
A2  
A3  
GND  
CLKAB  
B1  
GND  
B2  
1
56  
55  
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49  
48  
47  
46  
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43  
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37  
36  
35  
WidebusFamily  
2
3
4
5
B3  
6
D ESD Protection Exceeds 2000 V Per  
MIL-STD-883C, Method 3015; Exceeds  
200 V Using Machine Model (C = 200 pF,  
R = 0)  
V
V
7
CC  
CC  
A4  
A5  
A6  
GND  
A7  
B4  
B5  
B6  
GND  
B7  
8
9
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
D Latch-Up Performance Exceeds 250 mA  
Per JEDEC Standard JESD-17  
D Bus Hold on Data Inputs Eliminates the  
Need for External Pullup/Pulldown  
Resistors  
A8  
A9  
B8  
B9  
A10  
A11  
A12  
GND  
A13  
A14  
A15  
B10  
B11  
B12  
GND  
B13  
B14  
B15  
D Package Options Include Plastic 300-mil  
Shrink Small-Outline (DL) and Thin Shrink  
Small-Outline (DGG) Packages  
description  
The SN74ALVC16501 18-bit universal bus  
transceiver is designed for low-voltage (3.3-V)  
V
V
CC  
CC  
A16 23  
A17 24  
34 B16  
V
operation; it is tested at 2.5-V, 2.7-V, and  
CC  
33 B17  
3.3-V V  
.
CC  
GND 25  
A18 26  
32 GND  
31 B18  
Data flow in each direction is controlled by  
output-enable (OEAB and OEBA), latch-enable  
(LEAB and LEBA), and clock (CLKAB and  
CLKBA) inputs. For A-to-B data flow, the device  
operates in the transparent mode when LEAB is  
high. When LEAB is low, the A data is latched if  
CLKAB is held at a high or low logic level. If LEAB  
is low, the A-bus data is stored in the latch/flip-flop  
on the low-to-high transition of CLKAB. When  
OEAB is high, the outputs are active. When OEAB  
is low, the outputs are in the high-impedance  
state.  
OEBA 27  
LEBA 28  
30 CLKBA  
29 GND  
Data flow for B to A is similar to that of A to B but uses OEBA, LEBA, and CLKBA. The output enables are  
complementary (OEAB is active high and OEBA is active low).  
The SN74ALVC16501 is available in TI’s shrink small-outline (DL) and thin shrink small-outline (DGG)  
packages, which provide twice the I/O pin count and functionality of standard small-outline packages in the  
same printed-circuit-board area.  
The SN74ALVC16501 is characterized for operation from −40°C to 85°C.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
EPIC, UBT, and Widebus are trademarks of Texas Instruments Incorporated.  
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Copyright 1995, Texas Instruments Incorporated  
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1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443  
1234567...11

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 		ALVC/VCX/A SERIES, 18-BIT REGISTERED TRANSCEIVER, TRUE OUTPUT, PDSO56
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SN74ALVC16543DGG TI

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 		ALVC/VCX/A SERIES, 18-BIT REGISTERED TRANSCEIVER, TRUE OUTPUT, PDSO56
SN74ALVC16600DL TI

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 		ALVC/VCX/A SERIES, 18-BIT REGISTERED TRANSCEIVER, TRUE OUTPUT, PDSO56
SN74ALVC16600DLR TI

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 		ALVC/VCX/A SERIES, 18-BIT REGISTERED TRANSCEIVER, TRUE OUTPUT, PDSO56
SN74ALVC16601DGGR TI

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 		ALVC/VCX/A SERIES, 18-BIT REGISTERED TRANSCEIVER, TRUE OUTPUT, PDSO56

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