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ꢈ ꢌ ꢍꢎꢏ ꢐ ꢑꢁꢏ ꢆꢒ ꢓꢀꢄꢅ ꢎꢑꢀ ꢐ ꢓꢄꢁ ꢀꢇ ꢒ ꢏꢆ ꢒ ꢓ
ꢔ ꢏꢐ ꢕ ꢖ ꢍꢀꢐꢄꢐ ꢒ ꢗ ꢑꢐ ꢘꢑ ꢐꢀ
SCAS261A − JANUARY 1993 − REVISED JULY 1995
DGG OR DL PACKAGE
(TOP VIEW)
D EPIC (Enhanced-Performance Implanted
CMOS) Submicron Process
D Member of the Texas Instruments
D UBT (Universal Bus Transceiver)
Combines D-Type Latches and D-Type
Flip-Flops for Operation in Transparent,
Latched, or Clocked Mode
OEAB
LEAB
A1
GND
A2
A3
GND
CLKAB
B1
GND
B2
1
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
Widebus Family
2
3
4
5
B3
6
D ESD Protection Exceeds 2000 V Per
MIL-STD-883C, Method 3015; Exceeds
200 V Using Machine Model (C = 200 pF,
R = 0)
V
V
7
CC
CC
A4
A5
A6
GND
A7
B4
B5
B6
GND
B7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
D Latch-Up Performance Exceeds 250 mA
Per JEDEC Standard JESD-17
D Bus Hold on Data Inputs Eliminates the
Need for External Pullup/Pulldown
Resistors
A8
A9
B8
B9
A10
A11
A12
GND
A13
A14
A15
B10
B11
B12
GND
B13
B14
B15
D Package Options Include Plastic 300-mil
Shrink Small-Outline (DL) and Thin Shrink
Small-Outline (DGG) Packages
description
The SN74ALVC16501 18-bit universal bus
transceiver is designed for low-voltage (3.3-V)
V
V
CC
CC
A16 23
A17 24
34 B16
V
operation; it is tested at 2.5-V, 2.7-V, and
CC
33 B17
3.3-V V
.
CC
GND 25
A18 26
32 GND
31 B18
Data flow in each direction is controlled by
output-enable (OEAB and OEBA), latch-enable
(LEAB and LEBA), and clock (CLKAB and
CLKBA) inputs. For A-to-B data flow, the device
operates in the transparent mode when LEAB is
high. When LEAB is low, the A data is latched if
CLKAB is held at a high or low logic level. If LEAB
is low, the A-bus data is stored in the latch/flip-flop
on the low-to-high transition of CLKAB. When
OEAB is high, the outputs are active. When OEAB
is low, the outputs are in the high-impedance
state.
OEBA 27
LEBA 28
30 CLKBA
29 GND
Data flow for B to A is similar to that of A to B but uses OEBA, LEBA, and CLKBA. The output enables are
complementary (OEAB is active high and OEBA is active low).
The SN74ALVC16501 is available in TI’s shrink small-outline (DL) and thin shrink small-outline (DGG)
packages, which provide twice the I/O pin count and functionality of standard small-outline packages in the
same printed-circuit-board area.
The SN74ALVC16501 is characterized for operation from −40°C to 85°C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC, UBT, and Widebus are trademarks of Texas Instruments Incorporated.
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Copyright 1995, Texas Instruments Incorporated
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ꢡ ꢥ ꢢ ꢡꢚ ꢛꢯ ꢝꢜ ꢠ ꢨꢨ ꢦꢠ ꢞ ꢠ ꢟ ꢥ ꢡ ꢥ ꢞ ꢢ ꢪ
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1
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