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SN74ALVC16260DLR

更新时间： 2024-11-21 13:13:47
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德州仪器 - TI 锁存器输出元件
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SN74ALVC16260DLR 数据手册

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SCAS252A − OCTOBER 1993 − REVISED JULY 1995  
DGG OR DL PACKAGE  
(TOP VIEW)  
D EPIC (Enhanced-Performance Implanted  
CMOS) Submicron Process  
D Member of the Texas Instruments  
D ESD Protection Exceeds 2000 V Per  
MIL-STD-883C, Method 3015; Exceeds  
200 V Using Machine Model  
OEA  
LE1B  
2B3  
GND  
2B2  
OE2B  
LEA2B  
2B4  
GND  
2B5  
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2
3
4
5
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9
56  
55  
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52  
51  
50  
49  
48  
WidebusFamily  
(C = 200 pF, R = 0)  
2B1  
2B6  
D Latch-Up Performance Exceeds 250 mA  
V
V
CC  
CC  
Per JEDEC Standard JESD-17  
A1  
A2  
2B7  
2B8  
D Flow-Through Architecture Optimizes  
PCB Layout  
A3 10  
47 2B9  
GND  
A4  
GND  
2B10  
11  
12  
46  
45  
D Bus Hold on Data Inputs Eliminates  
the Need for External Pullup/Pulldown  
Resistors  
A5 13  
A6 14  
44 2B11  
43 2B12  
42 1B12  
41 1B11  
40 1B10  
39 GND  
38 1B9  
37 1B8  
36 1B7  
D Package Options Include Plastic Shrink  
Small-Outline (DL) and Thin Shrink  
Small-Outline (DGG) Packages  
A7 15  
A8 16  
A9 17  
GND 18  
A10 19  
A11 20  
A12 21  
description  
The SN74ALVC16260 is a 12-bit to 24-bit  
multiplexed D-type latch used in applications  
where two separate data paths must be  
multiplexed onto, or demultiplexed from, a single  
data path. Typical applications include  
multiplexing and/or demultiplexing address and  
data information in microprocessor or bus-  
interface applications. This device is also useful in  
memory-interleaving applications.  
V
22  
35  
V
CC  
CC  
1B1 23  
1B2 24  
GND 25  
1B3 26  
LE2B 27  
SEL 28  
34 1B6  
33 1B5  
32 GND  
31 1B4  
30 LEA1B  
29 OE1B  
Three 12-bit I/O ports (A1−A12, 1B1−1B12, and  
2B1−2B12) are available for address and/or data  
transfer. The output-enable (OE1B, OE2B, and  
OEA) inputs control the bus transceiver functions.  
The OE1B and OE2B control signals also allow  
bank control in the A-to-B direction.  
Address and/or data information can be stored using the internal storage latches. The latch-enable (LE1B,  
LE2B, LEA1B, and LEA2B) inputs are used to control data storage. When the latch-enable input is high, the  
latch is transparent. When the latch-enable input goes low, the data present at the inputs is latched and remains  
latched until the latch-enable input is returned high.  
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.  
The SN74ALVC16260 is available in TI’s shrink small-outline (DL) and thin shrink small-outline (DGG)  
packages, which provide twice the I/O pin count and functionality of standard small-outline packages in the  
same printed-circuit-board area.  
The SN74ALVC16260 is characterized for operation from −40°C to 85°C.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
EPIC and Widebus are trademarks of Texas Instruments Incorporated.  
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Copyright 1995, Texas Instruments Incorporated  
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1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443  
1234567...9

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