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SN74ALVC16269DL

更新时间： 2024-09-16 02:58:31
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德州仪器 - TI 输出元件
页数 文件大小 规格书
9页 164K
描述
12-BIT TO 24-BIT REGISTERED BUS TRANSCEIVER WITH 3-STATE OUTPUTS

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SN74ALVC16269DL 数据手册

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SCAS417B − OCTOBER 1993 − REVISED JULY 1995  
DGG OR DL PACKAGE  
(TOP VIEW)  
D EPIC (Enhanced-Performance Implanted  
CMOS) Submicron Process  
D Member of the Texas Instruments  
D ESD Protection Exceeds 2000 V Per  
MIL-STD-883C, Method 3015; Exceeds  
200 V Using Machine Model  
OEA  
OEB1  
2B3  
GND  
2B2  
1
56  
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50  
49  
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36  
35  
34  
33  
32  
31  
30  
29  
OEB2  
CLKENA2  
2B4  
GND  
2B5  
WidebusFamily  
2
3
4
5
(C = 200 pF, R = 0)  
2B1  
6
2B6  
D Latch-Up Performance Exceeds 250 mA  
V
7
V
CC  
CC  
Per JEDEC Standard JESD-17  
A1  
A2  
A3  
GND  
A4  
A5  
A6  
A7  
A8  
8
2B7  
2B8  
2B9  
D Bus Hold on Data Inputs Eliminates  
the Need for External Pullup/Pulldown  
Resistors  
9
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
GND  
2B10  
2B11  
2B12  
1B12  
1B11  
1B10  
GND  
1B9  
D Package Options Include Plastic Shrink  
Small-Outline (DL) and Thin Shrink  
Small-Outline (DGG) Packages  
description  
A9  
The SN74ALVC16269 is a 12-bit to 24-bit  
registered bus transceiver, which is intended  
for applications where two separate ports  
must be multiplexed onto, or demultiplexed  
from, a single port. The device is particularly  
suitable as an interface between synchronous  
DRAMs and high-speed microprocessors. The  
SN74ALVC16269 is designed specifically for  
GND  
A10  
A11  
A12  
1B8  
1B7  
V
V
CC  
CC  
1B1  
1B2  
GND  
1B3  
NC  
1B6  
1B5  
GND  
1B4  
CLKENA1  
CLK  
low-voltage (3.3-V) V  
2.5-V, 2.7-V, and 3.3-V V  
operation; it is tested at  
CC  
.
CC  
Data is stored in the internal B-port registers on  
the low-to-high transition of the clock (CLK) input  
when the appropriate clock-enable (CLKENA)  
inputs are low. Proper control of these inputs  
allows two sequential 12-bit words to be  
presented as a 24-bit word on the B port. For data  
SEL  
NC − No internal connection  
transfer in the B-to-A direction, a single storage register is provided. The select (SEL) line selects 1B or 2B data  
for the A outputs. The register on the A output permits the fastest possible data transfer, thus extending the  
period that the data is valid on the bus. The control terminals are registered so that all transactions are  
synchronous with CLK. Data flow is controlled by the active-low output enables (OEA, OEB1, OEB2).  
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.  
The SN74ALVC16269 is available in TI’s shrink small-outline (DL) and thin shrink small-outline (DGG)  
packages, which provide twice the I/O pin count and functionality of standard small-outline packages in the  
same printed-circuit-board area.  
The SN74ALVC16269 is characterized for operation from −40°C to 85°C.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
EPIC and Widebus are trademarks of Texas Instruments Incorporated.  
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Copyright 1995, Texas Instruments Incorporated  
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1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443  
1234567...9

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SN74ALVC16269DL 替代型号

型号 品牌 替代类型 描述 数据表
SN74ALVCH16269DL TI

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