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SN74ALVC162831DBB

更新时间： 2024-11-20 22:38:31
品牌 Logo 应用领域
德州仪器 - TI 驱动器输出元件双倍数据速率
页数 文件大小 规格书
9页 127K
描述
1-BIT TO 4-BIT ADDRESS REGISTER/DRIVER WITH 3-STATE OUTPUTS

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SN74ALVC162831DBB 技术参数

是否Rohs认证： 不符合生命周期：Obsolete
包装说明：TSSOP, TSSOP80,.3,16Reach Compliance Code：not_compliant
风险等级：5.92JESD-30 代码：R-PDSO-G80
逻辑集成电路类型：BUS DRIVER端子数量：80
最高工作温度：85 °C最低工作温度：-40 °C
封装主体材料：PLASTIC/EPOXY封装代码：TSSOP
封装等效代码：TSSOP80,.3,16封装形状：RECTANGULAR
封装形式：SMALL OUTLINE, THIN PROFILE, SHRINK PITCH电源：3.3 V
认证状态：Not Qualified子类别：Other Logic ICs
标称供电电压 (Vsup)：3.3 V表面贴装：YES
技术：CMOS温度等级：INDUSTRIAL
端子形式：GULL WING端子节距：0.4 mm
端子位置：DUALBase Number Matches：1

SN74ALVC162831DBB 数据手册

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SN74ALVC162831  
1-BIT TO 4-BIT ADDRESS REGISTER/DRIVER  
WITH 3-STATE OUTPUTS  
SCAS605A – APRIL 1998 – REVISED FEBRUARY 1999  
DBB PACKAGE  
(TOP VIEW)  
Member of the Texas Instruments  
Widebus Family  
EPIC (Enhanced-Performance Implanted  
CMOS) Submicron Process  
4Y1  
3Y1  
GND  
2Y1  
1Y2  
2Y2  
GND  
3Y2  
4Y2  
1
2
3
4
5
6
7
8
9
80  
79  
78  
77  
76  
75  
74  
73  
72  
Output Ports Have Equivalent 26-Ω Series  
Resistors, So No External Resistors Are  
Required  
1Y1  
ESD Protection Exceeds 2000 V Per  
MIL-STD-883, Method 3015; Exceeds 200 V  
Using Machine Model (C = 200 pF, R = 0)  
V
V
CC  
CC  
NC  
A1  
GND  
1Y3  
2Y3  
GND  
Latch-Up Performance Exceeds 250 mA Per  
JESD 17  
NC 10  
71 3Y3  
A2  
GND  
4Y3  
GND  
11  
12  
70  
69  
Packaged in Thin Very Small-Outline  
Package  
NC 13  
A3 14  
68 1Y4  
67 2Y4  
description  
V
15  
66  
V
CC  
CC  
This 1-bit to 4-bit address register/driver is  
designed for 1.65-V to 3.6-V V operation.  
NC 16  
A4 17  
65 3Y4  
64 4Y4  
63 GND  
62 1Y5  
61 2Y5  
60 3Y5  
59 4Y5  
58 GND  
57 1Y6  
56 2Y6  
CC  
GND 18  
CLK 19  
OE1 20  
OE2 21  
SEL 22  
GND 23  
A5 24  
The device is ideal for use in applications in which  
a single address bus is driving four separate  
memorylocations. TheSN74ALVC162831canbe  
used as a buffer or a register, depending on the  
logic level of the select (SEL) input.  
When SEL is logic high, the device is in the buffer  
mode. The outputs follow the inputs and are  
controlled by the two output-enable (OE) inputs.  
Each OE controls two groups of nine outputs.  
A6 25  
V
26  
A7 27  
55  
V
CC  
CC  
54 3Y6  
53 4Y6  
52 GND  
51 1Y7  
50 2Y7  
49 GND  
48 3Y7  
47 4Y7  
When SEL is logic low, the device is in the register  
mode. The register is an edge-triggered D-type  
flip-flop. On the positive transition of the clock  
(CLK) input, data set up at the A inputs is stored  
in the internal registers. OE controls operate the  
same as in buffer mode.  
NC 28  
GND 29  
A8 30  
NC 31  
GND 32  
A9 33  
NC 34  
When OE is logic low, the outputs are in a normal  
logic state (high or low logic level). When OE is  
logic high, the outputs are in the high-impedance  
state.  
V
35  
46  
V
CC  
CC  
4Y9 36  
3Y9 37  
GND 38  
2Y9 39  
1Y9 40  
45 1Y8  
44 2Y8  
43 GND  
42 3Y8  
41 4Y8  
SEL and OE do not affect the internal operation of  
the flip-flops. Old data can be retained or new data  
can be entered while the outputs are in the  
high-impedance state.  
NC – No internal connection  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
EPIC and Widebus are trademarks of Texas Instruments Incorporated.  
Copyright 1999, Texas Instruments Incorporated  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567...9

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