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SN74ALVC162836 PDF预览

SN74ALVC162836

更新时间: 2024-11-05 23:09:43
品牌 Logo 应用领域
德州仪器 - TI 总线驱动器输出元件
页数 文件大小 规格书
10页 137K
描述
20-BIT UNIVERSAL BUS DRIVER WITH 3-STATE OUTPUTS

SN74ALVC162836 数据手册

 浏览型号SN74ALVC162836的Datasheet PDF文件第2页浏览型号SN74ALVC162836的Datasheet PDF文件第3页浏览型号SN74ALVC162836的Datasheet PDF文件第4页浏览型号SN74ALVC162836的Datasheet PDF文件第5页浏览型号SN74ALVC162836的Datasheet PDF文件第6页浏览型号SN74ALVC162836的Datasheet PDF文件第7页 
SN74ALVC162836  
20-BIT UNIVERSAL BUS DRIVER  
WITH 3-STATE OUTPUTS  
SCES129B – MARCH 1998 – REVISED FEBRUARY 1999  
DGG, DGV, OR DL PACKAGE  
(TOP VIEW)  
Member of the Texas Instruments  
Widebus Family  
EPIC (Enhanced-Performance Implanted  
CMOS) Submicron Process  
OE  
Y1  
Y2  
GND  
Y3  
Y4  
1
2
3
4
5
6
7
8
9
10  
56 CLK  
55 A1  
54 A2  
53 GND  
52 A3  
51 A4  
Output Port Has Equivalent 26-Series  
Resistors, So No External Resistors Are  
Required  
Designed to Comply With JEDEC 168-Pin  
and 200-Pin SDRAM Buffered DIMM  
Specification  
V
50  
V
CC  
Y5  
CC  
49 A5  
48 A6  
Package Options Include Plastic Shrink  
Small-Outline (DL), Thin Shrink  
Small-Outline (DGG), and Thin Very  
Small-Outline (DGV) Packages  
Y6  
Y7  
GND 11  
Y8 12  
47  
A7  
46 GND  
45 A8  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
44  
43  
42  
41  
40  
39  
38  
37  
36  
35  
34  
33  
32  
31  
30  
29  
Y9  
Y10  
Y11  
Y12  
Y13  
GND  
Y14  
Y15  
Y16  
A9  
description  
A10  
A11  
A12  
A13  
GND  
A14  
A15  
A16  
This 20-bit universal bus driver is designed for  
1.65-V to 3.6-V V operation.  
CC  
Data flow from A to Y is controlled by the  
output-enable (OE) input. The device operates in  
the transparent mode when the latch-enable (LE)  
input is low. When LE is high, the A data is latched  
if the clock (CLK) input is held at a high or low logic  
level. If LE is high, the A data is stored in the  
latch/flip-flop on the low-to-high transition of CLK.  
When OE is high, the outputs are in the  
high-impedance state.  
V
V
CC  
CC  
Y17  
Y18  
GND  
Y19  
Y20  
NC  
A17  
A18  
GND  
A19  
A20  
LE  
The output port includes equivalent 26-series  
resistors to reduce overshoot and undershoot.  
To ensure the high-impedance state during power  
NC – No internal connection  
up or power down, OE should be tied to V  
CC  
through a pullup resistor; the minimum value of  
the resistor is determined by the current-sinking  
capability of the driver.  
The SN74ALVC162836 is characterized for  
operation from –40°C to 85°C.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
EPIC and Widebus are trademarks of Texas Instruments Incorporated.  
Copyright 1999, Texas Instruments Incorporated  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  

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