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SN74ALVC125_15

更新时间： 2024-11-19 02:58:47
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德州仪器 - TI 输出元件
页数 文件大小 规格书
15页 674K
描述
QUADRUPLE BUS BUFFER GATE WITH 3-STATE OUTPUTS

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SN74ALVC125_15 数据手册

 浏览型号SN74ALVC125_15的Datasheet PDF文件第2页浏览型号SN74ALVC125_15的Datasheet PDF文件第3页浏览型号SN74ALVC125_15的Datasheet PDF文件第4页浏览型号SN74ALVC125_15的Datasheet PDF文件第5页浏览型号SN74ALVC125_15的Datasheet PDF文件第6页浏览型号SN74ALVC125_15的Datasheet PDF文件第7页 
SN74ALVC125  
QUADRUPLE BUS BUFFER GATE  
WITH 3-STATE OUTPUTS  
www.ti.com  
SCES110H–JULY 1997–REVISED SEPTEMBER 2004  
FEATURES  
D, DGV, NS, OR PW PACKAGE  
(TOP VIEW)  
•
•
•
•
Operates from 1.65 V to 3.6 V  
Max tpd of 2.8 ns at 3.3 V  
1
2
3
4
5
6
7
14  
13  
12  
11  
10  
9
1OE  
1A  
V
CC  
±24-mA Output Drive at 3.3 V  
4OE  
4A  
4Y  
3OE  
3A  
3Y  
Latch-up Performance Exceeds 250 mA Per  
JESD 17  
1Y  
2OE  
2A  
2Y  
GND  
•
ESD Performance Exceeds JESD 22  
– 2000-V Human-Body Model (A114-A)  
– 200-V Machine Model (A115-A)  
8
– 1000-V Charged-Device Model (C101)  
DESCRIPTION/ORDERING INFORMATION  
This quadruple bus buffer gate is designed for 1.65-V to 3.6-V VCC operation.  
The SN74ALVC125 features independent line drivers with 3-state outputs. Each output is disabled when the  
associated output-enable (OE) input is high.  
To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup  
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.  
ORDERING INFORMATION  
TA  
PACKAGE(1)  
ORDERABLE PART NUMBER  
SN74ALVC125D  
TOP-SIDE MARKING  
ALVC125  
Tube  
SOIC - D  
Tape and reel  
SN74ALVC125DR  
SOP - NS  
Tape and reel  
Tube  
SN74ALVC125NSR  
SN74ALVC125PW  
ALVC125  
VA125  
-40°C to 85°C  
TSSOP - PW  
TVSOP - DGV  
Tape and reel  
Tape and reel  
SN74ALVC125PWR  
SN74ALVC125DGVR  
VA125  
(1) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at  
www.ti.com/sc/package.  
FUNCTION TABLE  
(each buffer)  
INPUTS  
OUTPUT  
Y
OE  
L
A
H
L
H
L
L
H
X
Z
LOGIC DIAGRAM (POSITIVE LOGIC)  
1
2
10  
1OE  
1A  
3OE  
9
8
3
6
3A  
3Y  
4Y  
1Y  
2Y  
4
5
13  
12  
2OE  
2A  
4OE  
4A  
11  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas  
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
PRODUCTION DATA information is current as of publication date.  
Copyright © 1997–2004, Texas Instruments Incorporated  
Products conform to specifications per the terms of the Texas  
Instruments standard warranty. Production processing does not  
necessarily include testing of all parameters.  
1234567...15

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