5秒后页面跳转
捷配首页

Datasheet > 逻辑 > 总线驱动器/收发器> SN74ALVC126DGV
SN74ALVC126DGV PDF预览

SN74ALVC126DGV

更新时间： 2024-11-20 23:09:43
品牌 Logo 应用领域
德州仪器 - TI 输出元件
页数 文件大小 规格书
8页 111K
描述
QUADRUPLE BUS BUFFER GATE WITH 3-STATE OUTPUTS

阅读下载

中文翻译

获取价格

SN74ALVC126DGV 数据手册

 浏览型号SN74ALVC126DGV的Datasheet PDF文件第2页浏览型号SN74ALVC126DGV的Datasheet PDF文件第3页浏览型号SN74ALVC126DGV的Datasheet PDF文件第4页浏览型号SN74ALVC126DGV的Datasheet PDF文件第5页浏览型号SN74ALVC126DGV的Datasheet PDF文件第6页浏览型号SN74ALVC126DGV的Datasheet PDF文件第7页 
SN74ALVC126  
QUADRUPLE BUS BUFFER GATE  
WITH 3-STATE OUTPUTS  
SCES111E – JULY 1997 – REVISED FEBRUARY 1999  
D, DGV, OR PW PACKAGE  
(TOP VIEW)  
EPIC (Enhanced-Performance Implanted  
CMOS) Submicron Process  
ESD Protection Exceeds 2000 V Per  
MIL-STD-883, Method 3015; Exceeds 200 V  
Using Machine Model (C = 200 pF, R = 0)  
1OE  
1A  
V
CC  
4OE  
4A  
1
2
3
4
5
6
7
14  
13  
12  
11  
1Y  
Latch-Up Performance Exceeds 250 mA Per  
JESD 17  
2OE  
2A  
4Y  
10 3OE  
Package Options Include Plastic  
Small-Outline (D), Thin Very Small-Outline  
(DGV), and Thin Shrink Small-Outline (PW)  
Packages  
2Y  
9
8
3A  
3Y  
GND  
description  
This quadruple bus buffer gate is designed for 1.65-V to 3.6-V V  
operation.  
CC  
The SN74ALVC126 features independent line drivers with 3-state outputs. Each output is disabled when the  
associated output-enable (OE) input is low.  
To ensure the high-impedance state during power up or power down, OE should be tied to GND through a  
pulldown resistor; the minimum value of the resistor is determined by the current-sourcing capability of  
the driver.  
The SN74ALVC126 is characterized for operation from –40°C to 85°C.  
FUNCTION TABLE  
(each buffer)  
INPUTS  
OUTPUT  
Y
OE  
A
H
L
H
H
L
H
L
X
Z
†
logic symbol  
1
1
1OE  
1A  
EN  
3
6
1Y  
2Y  
3Y  
4Y  
2
4
2OE  
5
2A  
3OE  
3A  
10  
9
8
13  
12  
4OE  
11  
4A  
†
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
EPIC is a trademark of Texas Instruments Incorporated.  
Copyright 1999, Texas Instruments Incorporated  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
12345678

中文翻译

下载PDF

与SN74ALVC126DGV相关器件

型号 品牌 获取价格 描述 数据表
SN74ALVC126DGVR TI

获取价格

 		具有三态输出的 4 通道、1.65V 至 3.6V 缓冲器 | DGV | 14 | -4
SN74ALVC126DGVRE4 TI

获取价格

 		Quadruple Bus Buffer Gate With 3-State Outputs 14-TVSOP -40 to 85
SN74ALVC126DGVRG4 TI

获取价格

 		ALVC/VCX/A SERIES, QUAD 1-BIT DRIVER, TRUE OUTPUT, PDSO14, GREEN, PLASTIC, TVSOP-14
SN74ALVC126DR TI

获取价格

 		Quadruple Bus Buffer Gate With 3-State Outputs 14-SOIC -40 to 85
SN74ALVC126NSR TI

获取价格

 		具有三态输出的 4 通道、1.65V 至 3.6V 缓冲器 | NS | 14 | -40
SN74ALVC126PW TI

获取价格

 		QUADRUPLE BUS BUFFER GATE WITH 3-STATE OUTPUTS
SN74ALVC126PWLE TI

获取价格

 		ALVC/VCX/A SERIES, QUAD 1-BIT DRIVER, TRUE OUTPUT, PDSO14, TSSOP-14
SN74ALVC126PWR TI

获取价格

 		具有三态输出的 4 通道、1.65V 至 3.6V 缓冲器 | PW | 14 | -40
SN74ALVC126PWRE4 TI

获取价格

 		具有三态输出的 4 通道、1.65V 至 3.6V 缓冲器 | PW | 14 | -40
SN74ALVC126PWRG4 TI

获取价格

 		Quadruple Bus Buffer Gate With 3-State Outputs 14-TSSOP -40 to 85

与SN74ALVC126DGV相关文章

您还可以找


热门产品
PCB打样/小批量
铝基板
BOM智能配单
PCBA制造
钣金
精密CNC
模具注塑
薄膜开关
精选活动
PCBA打样特惠
四六层板品质升级
铝基板品质升级
一体化电子制造
DFM下载
服务支持
企业认证
产品展示
工厂展示
工艺能力
积分商城
关于捷配
捷配简介
企业文化
公司动态
人才招聘
联系我们
帮助中心
下单流程
付款流程
开票流程
常见问题
全球PCB制造服务专线 400-613-0088

工作时间：9:00-21:00

CEO邮箱：ceo@jiepei.com

投诉邮箱：tousu@jiepei.com

捷配网-微信公众号 微信公众号
捷配网-微信公众号 抖音公众号
资质认证：
合作快递：
支付方式：
Copyright © 2024 Jiepei.com Inc. All Rights Reserved. 版权所有:杭州捷配信息科技有限公司 浙公网安备 33010502006866号 浙ICP备10014259号-119 营业执照ICP证