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SN74ALVC126DGVRG4 PDF预览

SN74ALVC126DGVRG4

更新时间: 2024-11-18 15:52:07
品牌 Logo 应用领域
德州仪器 - TI 驱动光电二极管输出元件逻辑集成电路电视
页数 文件大小 规格书
15页 645K
描述
ALVC/VCX/A SERIES, QUAD 1-BIT DRIVER, TRUE OUTPUT, PDSO14, GREEN, PLASTIC, TVSOP-14

SN74ALVC126DGVRG4 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Obsolete零件包装代码:SOIC
包装说明:TSSOP, TSSOP14,.25,16针数:14
Reach Compliance Code:unknownHTS代码:8542.39.00.01
风险等级:5.56控制类型:ENABLE HIGH
系列:ALVC/VCX/AJESD-30 代码:R-PDSO-G14
JESD-609代码:e4长度:4.4 mm
负载电容(CL):50 pF逻辑集成电路类型:BUS DRIVER
最大I(ol):0.024 A湿度敏感等级:1
位数:1功能数量:4
端口数量:2端子数量:14
最高工作温度:85 °C最低工作温度:-40 °C
输出特性:3-STATE输出极性:TRUE
封装主体材料:PLASTIC/EPOXY封装代码:TSSOP
封装等效代码:TSSOP14,.25,16封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH包装方法:TR
峰值回流温度(摄氏度):260电源:3.3 V
Prop。Delay @ Nom-Sup:3.1 ns传播延迟(tpd):5.6 ns
认证状态:Not Qualified座面最大高度:1.2 mm
子类别:Bus Driver/Transceivers最大供电电压 (Vsup):3.6 V
最小供电电压 (Vsup):1.65 V标称供电电压 (Vsup):1.8 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子面层:Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式:GULL WING端子节距:0.4 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:3.6 mmBase Number Matches:1

SN74ALVC126DGVRG4 数据手册

 浏览型号SN74ALVC126DGVRG4的Datasheet PDF文件第2页浏览型号SN74ALVC126DGVRG4的Datasheet PDF文件第3页浏览型号SN74ALVC126DGVRG4的Datasheet PDF文件第4页浏览型号SN74ALVC126DGVRG4的Datasheet PDF文件第5页浏览型号SN74ALVC126DGVRG4的Datasheet PDF文件第6页浏览型号SN74ALVC126DGVRG4的Datasheet PDF文件第7页 
SN74ALVC126  
QUADRUPLE BUS BUFFER GATE  
WITH 3-STATE OUTPUTS  
www.ti.com  
SCES111JJULY 1997REVISED OCTOBER 2004  
FEATURES  
D, DGV, NS, OR PW PACKAGE  
(TOP VIEW)  
Operates From 1.65 V to 3.6 V  
Max tpd of 3.1 ns at 3.3 V  
1OE  
1A  
V
CC  
1
2
3
4
5
6
7
14  
13  
±24-mA Output Drive at 3.3 V  
4OE  
Latch-Up Performance Exceeds 250 mA Per  
JESD 17  
1Y  
12 4A  
11 4Y  
2OE  
2A  
ESD Performance Tested Per JESD 22  
– 2000-V Human-Body Model (A114-A)  
– 200-V Machine Model (A115-A)  
10  
9
3OE  
3A  
2Y  
8
GND  
3Y  
– 1000-V Charged-Device Model (C101)  
DESCRIPTION/ORDERING INFORMATION  
This quadruple bus buffer gate is designed for 1.65-V to 3.6-V VCC operation.  
The SN74ALVC126 features independent line drivers with 3-state outputs. Each output is disabled when the  
associated output-enable (OE) input is low.  
To ensure the high-impedance state during power up or power down, OE should be tied to GND through a  
pulldown resistor; the minimum value of the resistor is determined by the current-sourcing capability of the driver.  
ORDERING INFORMATION  
TA  
PACKAGE(1)  
ORDERABLE PART NUMBER  
SN74ALVC126D  
TOP-SIDE MARKING  
ALVC126  
Tube  
SOIC – D  
Tape and reel  
SN74ALVC126DR  
-40°C to 85°C  
SOP – NS  
Tape and reel  
Tape and reel  
Tape and reel  
SN74ALVC126NSR  
SN74ALVC126PWR  
SN74ALVC126DGVR  
ALVC126  
VA126  
TSSOP – PW  
TVSOP – DGV  
VA126  
(1) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at  
www.ti.com/sc/package.  
FUNCTION TABLE  
(each buffer)  
INPUTS  
OUTPUT  
Y
OE  
H
A
H
L
H
L
H
L
X
Z
LOGIC DIAGRAM (POSITIVE LOGIC)  
1
2
10  
1OE  
1A  
3OE  
3
6
9
8
1Y  
2Y  
3A  
3Y  
4Y  
4
5
13  
12  
2OE  
2A  
4OE  
4A  
11  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas  
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
PRODUCTION DATA information is current as of publication date.  
Copyright © 1997–2004, Texas Instruments Incorporated  
Products conform to specifications per the terms of the Texas  
Instruments standard warranty. Production processing does not  
necessarily include testing of all parameters.  

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