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SN74ALVC162268DLR

更新时间： 2024-11-21 11:58:39
品牌 Logo 应用领域
德州仪器 - TI 总线驱动器总线收发器逻辑集成电路光电二极管输出元件
页数 文件大小 规格书
11页 199K
描述
12-BIT TO 24-BIT REGISTERED BUS EXCHANGER WITH 3-STATE OUTPUTS

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中文翻译

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SN74ALVC162268DLR 技术参数

是否无铅： 含铅是否Rohs认证： 不符合
生命周期：Obsolete零件包装代码：SSOP
包装说明：SSOP, SSOP56,.4针数：56
Reach Compliance Code：not_compliant风险等级：5.57
系列：ALVC/VCX/AJESD-30 代码：R-PDSO-G56
长度：18.415 mm逻辑集成电路类型：BUS EXCHANGER
位数：12功能数量：1
端口数量：3端子数量：56
最高工作温度：85 °C最低工作温度：-40 °C
输出特性：3-STATE WITH SERIES RESISTOR输出极性：TRUE
封装主体材料：PLASTIC/EPOXY封装代码：SSOP
封装等效代码：SSOP56,.4封装形状：RECTANGULAR
封装形式：SMALL OUTLINE, SHRINK PITCH峰值回流温度（摄氏度）：NOT SPECIFIED
电源：2.5/3.3 V传播延迟（tpd）：5.9 ns
认证状态：Not Qualified座面最大高度：2.79 mm
子类别：Other Logic ICs最大供电电压 (Vsup)：3.6 V
最小供电电压 (Vsup)：2.3 V标称供电电压 (Vsup)：3.3 V
表面贴装：YES技术：CMOS
温度等级：INDUSTRIAL端子形式：GULL WING
端子节距：0.635 mm端子位置：DUAL
处于峰值回流温度下的最长时间：NOT SPECIFIED宽度：7.5 mm
Base Number Matches：1

SN74ALVC162268DLR 数据手册

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SCES051 − AUGUST 1995  
DGG OR DL PACKAGE  
(TOP VIEW)  
D B-Port Outputs Have Equivalent 26-Ω  
Series Resistors, So No External Resistors  
Are Required  
OEA  
OEB  
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D EPIC (Enhanced-Performance Implanted  
CLKEN1B  
2B3  
CLKENA2  
2B4  
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CMOS) Submicron Process  
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D Member of the Texas Instruments  
GND  
2B2  
GND  
2B5  
4
WidebusFamily  
5
D ESD Protection Exceeds 2000 V Per  
MIL-STD-883C, Method 3015; Exceeds  
200 V Using Machine Model  
2B1  
2B6  
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CC  
CC  
A1  
2B7  
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(C = 200 pF, R = 0)  
A2  
2B8  
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D Latch-Up Performance Exceeds 250 mA  
A3  
GND  
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A9  
GND  
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A12  
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Per JEDEC Standard JESD-17  
GND  
2B10  
2B11  
2B12  
1B12  
1B11  
1B10  
GND  
1B9  
D Bus Hold on Data Inputs Eliminates  
the Need for External Pullup/Pulldown  
Resistors  
D Package Options Include Plastic Shrink  
Small-Outline (DL) and Thin Shrink  
Small-Outline (DGG) Packages  
description  
1B8  
1B7  
The SN74ALVC162268 is a 12-bit to 24-bit  
registered bus exchanger, which is intended for  
use in applications where data must be  
transferred from a narrow high-speed bus to a  
wide, lower-frequency bus. This device is  
V
V
CC  
1B1  
CC  
1B6  
1B5  
GND  
1B4  
CLKENA1  
CLK  
1B2  
GND  
1B3  
CLKEN2B  
SEL  
designed specifically for low-voltage (3.3-V) V  
operation; it is tested at 2.5-V, 2.7-V, and 3.3-V  
CC  
V
.
CC  
The device provides synchronous data exchange  
between the two ports. Data is stored in the  
internal registers on the low-to-high transition of  
the clock (CLK) input when the appropriate  
clock-enable (CLKEN) inputs are low. The select  
(SEL) line is synchronous with CLK and selects  
1B or 2B input data for the A outputs.  
For data transfer in the A-to-B direction, a two-stage pipeline is provided in the A-to-1B path with a single storage  
register in the A-to-2B path. Proper control of these inputs allows two sequential 12-bit words to be presented  
synchronously as a 24-bit word on the B port. Data flow is controlled by the active-low output enables (OEA,  
OEB). These control terminals are registered so bus direction changes are synchronous with CLK.  
The B outputs, which are designed to sink up to 12 mA, include 26-Ω resistors to reduce overshoot and  
undershoot.  
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.  
The SN74ALVC162268 is characterized for operation from −40°C to 85°C.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
EPIC and Widebus are trademarks of Texas Instruments Incorporated.  
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Copyright 1995, Texas Instruments Incorporated  
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1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443  
1234567...11

中文翻译

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SN74ALVC162268DLR 替代型号

型号 品牌 替代类型 描述 数据表
SN74ALVCH162268DL TI

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