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SN74ALVC126PW

更新时间： 2024-11-17 22:34:31

品牌	Logo	应用领域
德州仪器 - TI		输出元件
页数	文件大小	规格书
8页	111K
描述
QUADRUPLE BUS BUFFER GATE WITH 3-STATE OUTPUTS

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数据手册

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SN74ALVC126PW 数据手册

SN74ALVC126

QUADRUPLE BUS BUFFER GATE

WITH 3-STATE OUTPUTS

SCES111E – JULY 1997 – REVISED FEBRUARY 1999

D, DGV, OR PW PACKAGE

(TOP VIEW)

EPIC (Enhanced-Performance Implanted

CMOS) Submicron Process

ESD Protection Exceeds 2000 V Per

MIL-STD-883, Method 3015; Exceeds 200 V

Using Machine Model (C = 200 pF, R = 0)

1OE

4OE

Latch-Up Performance Exceeds 250 mA Per

JESD 17

2OE

10 3OE

Package Options Include Plastic

Small-Outline (D), Thin Very Small-Outline

(DGV), and Thin Shrink Small-Outline (PW)

Packages

GND

description

This quadruple bus buffer gate is designed for 1.65-V to 3.6-V V

operation.

The SN74ALVC126 features independent line drivers with 3-state outputs. Each output is disabled when the

associated output-enable (OE) input is low.

To ensure the high-impedance state during power up or power down, OE should be tied to GND through a

pulldown resistor; the minimum value of the resistor is determined by the current-sourcing capability of

the driver.

The SN74ALVC126 is characterized for operation from –40°C to 85°C.

FUNCTION TABLE

(each buffer)

INPUTS

OUTPUT

†

logic symbol

1OE

2OE

3OE

4OE

†

This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

EPIC is a trademark of Texas Instruments Incorporated.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

12 3 4 5 6 7 8

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