SN74ALS112A

更新时间： 2024-11-23 23:06:15

品牌	Logo	应用领域
德州仪器 - TI		触发器
页数	文件大小	规格书
6页	99K
描述
DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET

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替代型号

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SN74ALS112A 数据手册

SN54ALS112A, SN74ALS112A

DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS

WITH CLEAR AND PRESET

SDAS199A – APRIL 1982 – REVISED DECEMBER 1994

SN54ALS112A . . . J PACKAGE

SN74ALS112A . . . D OR N PACKAGE

(TOP VIEW)

• Fully Buffered to Offer Maximum Isolation

From External Disturbance

• Package Options Include Plastic

Small-Outline (D) Packages, Ceramic Chip

Carriers (FK), and Standard Plastic (N) and

Ceramic (J) 300-mil DIPs

1CLK

1CLR

2CLR

2CLK

1PRE

TYPICAL MAXIMUM TYPICAL POWER

CLOCK

FREQUENCY

(MHz)

DISSIPATION

PER FLIP-FLOP

(mW)

TYPE

11 2J

2PRE

GND

′ALS112A

description

SN54ALS112A . . . FK PACKAGE

(TOP VIEW)

These devices contain two independent J-K

negative-edge-triggered flip-flops. A low level at

the preset (PRE) or clear (CLR) inputs sets or

resets the outputs, regardless of the levels of the

other inputs. When PRE and CLR are inactive

(high), data at the J and K inputs meeting the

setup-time requirements is transferred to the

outputs on the negative-going edge of the clock

pulse (CLK). Clock triggering occurs at a voltage

level and is not directly related to the fall time of the

clock pulse. Following the hold-time interval, data

at the J and K inputs may be changed without

affecting the levels at the outputs. These versatile

flip-flops can perform as toggle flip-flops by tying

J and K high.

1 20 19

1PRE

2CLR

2CLK

9 10 11 12 13

NC – No internal connection

The SN54ALS112A is characterized for operation over the full military temperature range of –55°C to 125°C.

The SN74ALS112A is characterized for operation from 0°C to 70°C.

FUNCTION TABLE

(each flip-flop)

INPUTS

OUTPUTS

PRE

CLR

CLK

†

↓

Toggle

†

The output levels in this configuration may not meet the

minimum levels for V . Furthermore, this configuration is

nonstable; that is, it does not persist when either PRE or

CLR returns to its inactive (high) level.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

12 3 4 5 6

中文翻译

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SN74ALS112A 替代型号

型号	品牌	替代类型	描述	数据表
SN54ALS112A	TI	功能相似	DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET

与SN74ALS112A相关器件

型号	品牌	获取价格	描述	数据表
SN74ALS112AD	TI	获取价格	DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET
SN74ALS112ADE4	TI	获取价格	ALS SERIES, DUAL NEGATIVE EDGE TRIGGERED J-K FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO16, GREE
SN74ALS112ADR	TI	获取价格	Dual J-K Negative-Edge-Triggered Flip-Flops With Clear and Preset 16-SOIC 0 to 70
SN74ALS112AFN	TI	获取价格	IC,FLIP-FLOP,DUAL,J/K TYPE,ALS-TTL,LDCC,20PIN,PLASTIC
SN74ALS112AFN-00	TI	获取价格	ALS SERIES, DUAL NEGATIVE EDGE TRIGGERED J-K FLIP-FLOP, COMPLEMENTARY OUTPUT, PQCC20
SN74ALS112AJ	TI	获取价格	IC,FLIP-FLOP,DUAL,J/K TYPE,ALS-TTL,DIP,16PIN,CERAMIC
SN74ALS112AJ4	TI	获取价格	IC,FLIP-FLOP,DUAL,J/K TYPE,ALS-TTL,DIP,16PIN,CERAMIC
SN74ALS112AJP4	TI	获取价格	IC,FLIP-FLOP,DUAL,J/K TYPE,ALS-TTL,DIP,16PIN,CERAMIC
SN74ALS112AN	TI	获取价格	DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET
SN74ALS112AN3	TI	获取价格	DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET

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