Datasheet > SN74ALS113ADR

SN74ALS113ADR

更新时间： 2024-09-17 02:58:47

品牌	Logo	应用领域
德州仪器 - TI		/
页数	文件大小	规格书
4页	55K
描述
DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS WITH PRESET

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SN74ALS113ADR 数据手册

SN54ALS113A, SN74ALS113A

DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS

WITH PRESET

SDAS200 – D2661, APRIL 1982 – REVISED MAY 1986

• Fully Buffered to Offer Maximum isolation

SN54ALS113A . . . J PACKAGE

SN74ALS113A . . . D OR N PACKAGE

from External Disturbance

(TOP VIEW)

• Package Options Include Plastic Small

Outline Packages, Ceramic Chip Carriers,

and Standard Plastic and Ceramic 300-mil

DIPs

1 CLK

1PRE

2CLK

2PRE

• Dependable Texas Instruments Quality and

Reliability

GND

TYPICAL POWER

DISSIPATION

PER FLIP-FLOP

TYPICAL MAXIMUM

CLOCK FREQUENCY

TYPE

’ALS113A

40 MHz (C =15 pF)

6 mW

SN54ALS113A . . . FK PACKAGE

(TOP VIEW)

description

These devices contain two independent J-K

negative-edge-triggered flip-flops. A low level at

the Preset input sets the outputs regardless of the

levels of the other inputs. When Preset PRE is

inactive (high), data at the J and K inputs meeting

the setup time requirements are transferred to the

outputs on the negative-going edge of the clock

pulse. Clock triggering occurs at a voltage level

and is not directly related to the fall time of the

clock pulse. Following the hold time interval, data

at the J and K inputs may be changed without

affecting the levels at the outputs. These versatile

flip-flops can perform as toggle flip-flops by tying

J and K high.

20 19

1PRE

2PRE

9 10 11 12 13

NC–No internal connection

†

logic symbol

The SN54ALS113A is characterized for operation

over the full military temperature range of –55°C

to 125°C. The SN74ALS113A is characterized for

operation from 0°C to 70°C.

1PRE

1CLK

FUNCTION TABLE

INPUTS

OUTPUTS

PRE

CLK

2PRE

↓

2CLK

↓

TOGGLE

†

This symbol is in accordance with ANSI/IEEE Std 91-1984 and

IEC Publication 617-12.

Pin numbers shown are for D, J, and N packages.

5BASIC

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

12 3 4

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与SN74ALS113ADR相关器件

型号	品牌	获取价格	描述	数据表
SN74ALS113AFN	TI	获取价格	IC,FLIP-FLOP,DUAL,J/K TYPE,ALS-TTL,LDCC,20PIN,PLASTIC
SN74ALS113AFN-00	TI	获取价格	ALS SERIES, DUAL NEGATIVE EDGE TRIGGERED J-K FLIP-FLOP, COMPLEMENTARY OUTPUT, PQCC20
SN74ALS113AJ4	TI	获取价格	IC,FLIP-FLOP,DUAL,J/K TYPE,ALS-TTL,DIP,14PIN,CERAMIC
SN74ALS113AJP4	TI	获取价格	IC,FLIP-FLOP,DUAL,J/K TYPE,ALS-TTL,DIP,14PIN,CERAMIC
SN74ALS113AN	ROCHESTER	获取价格	J-K Flip-Flop, ALS Series, 2-Func, Negative Edge Triggered, 2-Bit, Complementary Output, T
SN74ALS113AN	TI	获取价格	Dual J-K Negative-Edge-Triggered Flip-Flops With Preset 14-PDIP 0 to 70
SN74ALS113AN-10	TI	获取价格	ALS SERIES, DUAL NEGATIVE EDGE TRIGGERED J-K FLIP-FLOP, COMPLEMENTARY OUTPUT, PDIP14
SN74ALS113AN3	TI	获取价格	IC,FLIP-FLOP,DUAL,J/K TYPE,ALS-TTL,DIP,14PIN,PLASTIC
SN74ALS113ANP1	TI	获取价格	IC,FLIP-FLOP,DUAL,J/K TYPE,ALS-TTL,DIP,14PIN,PLASTIC
SN74ALS113ANP3	TI	获取价格	IC,FLIP-FLOP,DUAL,J/K TYPE,ALS-TTL,DIP,14PIN,PLASTIC

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