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SN74ALS112AN3

更新时间： 2024-11-25 02:58:15
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德州仪器 - TI /
页数 文件大小 规格书
6页 99K
描述
DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET

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SN74ALS112AN3 数据手册

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SN54ALS112A, SN74ALS112A  
DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS  
WITH CLEAR AND PRESET  
SDAS199A – APRIL 1982 – REVISED DECEMBER 1994  
SN54ALS112A . . . J PACKAGE  
SN74ALS112A . . . D OR N PACKAGE  
(TOP VIEW)  
• Fully Buffered to Offer Maximum Isolation  
From External Disturbance  
• Package Options Include Plastic  
Small-Outline (D) Packages, Ceramic Chip  
Carriers (FK), and Standard Plastic (N) and  
Ceramic (J) 300-mil DIPs  
1CLK  
1K  
V
CC  
1
2
3
4
5
6
7
8
16  
15  
14  
13  
12  
1CLR  
2CLR  
2CLK  
2K  
1J  
1PRE  
1Q  
TYPICAL MAXIMUM TYPICAL POWER  
CLOCK  
FREQUENCY  
(MHz)  
DISSIPATION  
PER FLIP-FLOP  
(mW)  
TYPE  
1Q  
11 2J  
10  
9
2Q  
2PRE  
2Q  
GND  
′ALS112A  
50  
6
description  
SN54ALS112A . . . FK PACKAGE  
(TOP VIEW)  
These devices contain two independent J-K  
negative-edge-triggered flip-flops. A low level at  
the preset (PRE) or clear (CLR) inputs sets or  
resets the outputs, regardless of the levels of the  
other inputs. When PRE and CLR are inactive  
(high), data at the J and K inputs meeting the  
setup-time requirements is transferred to the  
outputs on the negative-going edge of the clock  
pulse (CLK). Clock triggering occurs at a voltage  
level and is not directly related to the fall time of the  
clock pulse. Following the hold-time interval, data  
at the J and K inputs may be changed without  
affecting the levels at the outputs. These versatile  
flip-flops can perform as toggle flip-flops by tying  
J and K high.  
3
2
1 20 19  
18  
1J  
1PRE  
NC  
4
5
6
7
8
2CLR  
2CLK  
NC  
17  
16  
15  
14  
1Q  
2K  
1Q  
2J  
9 10 11 12 13  
NC – No internal connection  
The SN54ALS112A is characterized for operation over the full military temperature range of –55°C to 125°C.  
The SN74ALS112A is characterized for operation from 0°C to 70°C.  
FUNCTION TABLE  
(each flip-flop)  
INPUTS  
OUTPUTS  
PRE  
L
CLR  
H
CLK  
X
J
X
X
X
L
K
X
X
X
L
Q
H
L
Q
L
H
L
X
H
†
H
†
L
L
X
H
H
H
↓
Q
Q
0
0
H
H
↓
H
L
L
H
L
H
H
↓
H
H
X
L
H
H
H
↓
H
X
Toggle  
H
H
H
Q
Q
0
0
†
The output levels in this configuration may not meet the  
minimum levels for V . Furthermore, this configuration is  
nonstable; that is, it does not persist when either PRE or  
CLR returns to its inactive (high) level.  
OH  
Copyright 1994, Texas Instruments Incorporated  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
123456

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SN74ALS112AN3 替代型号

型号 品牌 替代类型 描述 数据表
8400002EA TI

完全替代

 具有清零和预置端的双路负边沿触发式 J-K 触发器 | J | 16 | -55 to 1
SNJ54ALS112AJ TI

完全替代

 具有清零和预置端的双路负边沿触发式 J-K 触发器 | J | 16 | -55 to 1
SN74ALS112AN TI

完全替代

 DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET

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