SN74ACT3641
1024 × 36
CLOCKED FIRST-IN, FIRST-OUT MEMORY
SCAS338C – JANUARY 1994 – REVISED OCTOBER 1997
Free-Running CLKA and CLKB Can Be
Asynchronous or Coincident
Output-Ready and Almost-Empty Flags
Synchronized by CLKB
Clocked FIFO Buffering Data From Port A
to Port B
Low-Power 0.8-µm Advanced CMOS
Technology
Memory Size: 1024 × 36
Supports Clock Frequencies up to 67 MHz
Fast Access Times of 11 ns
Synchronous Read-Retransmit Capability
Mailbox Register in Each Direction
Pin-to-Pin Compatible With the
SN74ACT3631 and SN74ACT3651
Programmable Almost-Full and
Almost-Empty Flags
Package Options Include 120-Pin Thin
Quad Flat (PCB) and 132-Pin Plastic Quad
Flat (PQ) Packages
Microprocessor Interface Control Logic
Input-Ready and Almost-Full Flags
Synchronized by CLKA
description
The SN74ACT3641 is a high-speed, low-power, CMOS clocked FIFO memory. It supports clock frequencies
up to 67 MHz and has read access times as fast as 12 ns. The 1024 × 36 dual-port SRAM FIFO buffers data
from port A to port B. The FIFO memory has retransmit capability, which allows previously read data to be
accessed again. The FIFO has flags to indicate empty and full conditions and two programmable flags (almost
full and almost empty) to indicate when a selected number of words is stored in memory. Communication
between each port takes place with two 36-bit mailbox registers. Each mailbox register has a flag to signal when
new mail has been stored. Two or more devices are used in parallel to create wider datapaths. Expansion is
also possible in word depth.
The SN74ACT3641 is a clocked FIFO, which means each port employs a synchronous interface. All data
transfersthroughaportaregatedtothelow-to-hightransitionofacontinuous(free-running)portclockbyenable
signals. The continuous clocks for each port are independent of one another and can be asynchronous or
coincident. The enables for each port are arranged to provide a simple interface between microprocessors
and/or buses with synchronous control.
The input-ready (IR) flag and almost-full (AF) flag of the FIFO are two-stage synchronized to CLKA. The
output-ready (OR) flag and almost-empty (AE) flag of the FIFO are two-stage synchronized to CLKB. Offset
values for the AF and AE flags of the FIFO can be programmed from port A or through a serial input.
The SN74ACT3641 is characterized for operation from 0°C to 70°C.
For more information on this device family, see the following application reports:
•
•
•
FIFO Patented Synchronous Retransmit: Programmable DSP-Interface Application for FIR Filtering
(literature number SCAA009)
FIFO Mailbox-Bypass Registers: Using Bypass Registers to Initialize DMA Control
(literature number SCAA007)
Metastability Performance of Clocked FIFOs (literature number SCZA004)
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Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 1997, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
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