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SN74ACT373MDWREP

更新时间： 2024-11-14 12:15:03
品牌 Logo 应用领域
德州仪器 - TI 总线驱动器总线收发器锁存器逻辑集成电路光电二极管输出元件
页数 文件大小 规格书
9页 284K
描述
OCTAL D-TYPE TRANSPARENT LATCH WITH 3-STATE OUTPUTS

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中文翻译

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SN74ACT373MDWREP 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Active零件包装代码：SOIC
包装说明：SOP, SOP20,.4针数：20
Reach Compliance Code：compliantECCN代码：EAR99
HTS代码：8542.39.00.01Factory Lead Time：6 weeks
风险等级：0.8控制类型：ENABLE LOW/HIGH
系列：ACTJESD-30 代码：R-PDSO-G20
JESD-609代码：e4长度：12.8 mm
负载电容（CL）：50 pF逻辑集成电路类型：BUS DRIVER
最大I（ol）：0.024 A湿度敏感等级：1
位数：8功能数量：1
端口数量：2端子数量：20
最高工作温度：125 °C最低工作温度：-55 °C
输出特性：3-STATE输出极性：TRUE
封装主体材料：PLASTIC/EPOXY封装代码：SOP
封装等效代码：SOP20,.4封装形状：RECTANGULAR
封装形式：SMALL OUTLINE包装方法：TR
峰值回流温度（摄氏度）：260电源：5 V
最大电源电流（ICC）：0.04 mAProp。Delay @ Nom-Sup：12.5 ns
传播延迟（tpd）：12.5 ns认证状态：Not Qualified
座面最大高度：2.65 mm子类别：FF/Latches
最大供电电压 (Vsup)：5.5 V最小供电电压 (Vsup)：4.5 V
标称供电电压 (Vsup)：5 V表面贴装：YES
技术：CMOS温度等级：MILITARY
端子面层：Nickel/Palladium/Gold (Ni/Pd/Au)端子形式：GULL WING
端子节距：1.27 mm端子位置：DUAL
处于峰值回流温度下的最长时间：NOT SPECIFIED翻译：N/A
宽度：7.5 mmBase Number Matches：1

SN74ACT373MDWREP 数据手册

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SCAS726 − OCTOBER 2003  
D
Controlled Baseline  
− One Assembly/Test Site, One Fabrication  
Site  
D
D
D
Inputs Accept Voltages to 5.5 V  
Max t of 10 ns at 5 V  
pd  
Inputs Are TTL-Voltage Compatible  
D
D
Extended Temperature Performance of  
−55°C to 125°C  
Enhanced Diminishing Manufacturing  
Sources (DMS) Support  
DW PACKAGE  
(TOP VIEW)  
1
2
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4
5
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8
9
10  
20  
19  
18  
17  
16  
15  
14  
13  
12  
11  
OE  
1Q  
1D  
2D  
2Q  
3Q  
3D  
4D  
4Q  
V
CC  
D
D
D
Enhanced Product-Change Notification  
8Q  
8D  
7D  
7Q  
6Q  
6D  
5D  
5Q  
LE  
†
Qualification Pedigree  
4.5-V to 5.5-V V  
Operation  
CC  
†
Component qualification in accordance with JEDEC and industry  
standards to ensure reliable operation over an extended  
temperature range. This includes, but is not limited to, Highly  
Accelerated Stress Test (HAST) or biased 85/85, temperature  
cycle, autoclave or unbiased HAST, electromigration, bond  
intermetallic life, and mold compound life. Such qualification  
testing should not be viewed as justifying use of this component  
beyond specified performance and environmental limits.  
GND  
description/ordering information  
This 8-bit latch features 3-state outputs designed specifically for driving highly capacitive or relatively  
low-impedance loads. The device is particularly suitable for implementing buffer registers, I/O ports,  
bidirectional bus drivers, and working registers.  
The eight latches are D-type transparent latches. When the latch-enable (LE) input is high, the Q outputs follow  
the data (D) inputs. When LE is taken low, the Q outputs are latched at the logic levels set up at the D inputs.  
A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high  
or low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive  
the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines  
in bus-organized systems without need for interface or pullup components.  
OE does not affect the internal operations of the latches. Old data can be retained or new data can be entered  
while the outputs are in the high-impedance state.  
To ensure the high-impedance state during power up or power down, OE should be tied to V  
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.  
through a pullup  
CC  
ORDERING INFORMATION  
ORDERABLE  
PART NUMBER  
TOP-SIDE  
MARKING  
‡
T
A
PACKAGE  
−55°C to 125°C  
SOIC − DW  
Tape and reel  
SN74ACT373MDWREP  
SACT373MEP  
‡
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are  
available at www.ti.com/sc/package.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
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Copyright 2003, Texas Instruments Incorporated  
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1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567...9

中文翻译

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SN74ACT373MDWREP 替代型号

型号 品牌 替代类型 描述 数据表
SN74ACT373DWR TI

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