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SN74ACT373DWR PDF预览

SN74ACT373DWR

更新时间： 2024-01-21 15:40:40
品牌 Logo 应用领域
德州仪器 - TI 锁存器输出元件
页数 文件大小 规格书
19页 583K
描述
OCTAL D-TYPE TRANSPARENT LATCHES WITH 3-STATE OUTPUTS

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中文翻译

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SN74ACT373DWR 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Active零件包装代码：TSSOP
包装说明：TSSOP, TSSOP20,.25针数：20
Reach Compliance Code：compliantECCN代码：EAR99
HTS代码：8542.39.00.01Factory Lead Time：1 week
风险等级：0.75控制类型：ENABLE LOW
计数方向：UNIDIRECTIONAL系列：ACT
JESD-30 代码：R-PDSO-G20JESD-609代码：e4
长度：6.5 mm负载电容（CL）：50 pF
逻辑集成电路类型：BUS DRIVER最大I（ol）：0.024 A
湿度敏感等级：1位数：8
功能数量：1端口数量：2
端子数量：20最高工作温度：85 °C
最低工作温度：-40 °C输出特性：3-STATE
输出极性：TRUE封装主体材料：PLASTIC/EPOXY
封装代码：TSSOP封装等效代码：TSSOP20,.25
封装形状：RECTANGULAR封装形式：SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
包装方法：TR峰值回流温度（摄氏度）：260
电源：5 V最大电源电流（ICC）：0.04 mA
Prop。Delay @ Nom-Sup：11.5 ns传播延迟（tpd）：11.5 ns
认证状态：Not Qualified座面最大高度：1.2 mm
子类别：FF/Latches最大供电电压 (Vsup)：5.5 V
最小供电电压 (Vsup)：4.5 V标称供电电压 (Vsup)：5 V
表面贴装：YES技术：CMOS
温度等级：INDUSTRIAL端子面层：Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式：GULL WING端子节距：0.65 mm
端子位置：DUAL处于峰值回流温度下的最长时间：NOT SPECIFIED
宽度：4.4 mm

SN74ACT373DWR 数据手册

 浏览型号SN74ACT373DWR的Datasheet PDF文件第2页浏览型号SN74ACT373DWR的Datasheet PDF文件第3页浏览型号SN74ACT373DWR的Datasheet PDF文件第4页浏览型号SN74ACT373DWR的Datasheet PDF文件第5页浏览型号SN74ACT373DWR的Datasheet PDF文件第6页浏览型号SN74ACT373DWR的Datasheet PDF文件第7页 
SN54ACT373, SN74ACT373  
OCTAL D-TYPE TRANSPARENT LATCHES  
WITH 3-STATE OUTPUTS  
SCAS544E – OCTOBER 1995 – REVISED OCTOBER 2002  
SN54ACT373 . . . J OR W PACKAGE  
SN74ACT373 . . . DB, DW, N, NS, OR PW PACKAGE  
(TOP VIEW)  
4.5-V to 5.5-V V  
Operation  
CC  
Inputs Accept Voltages to 5.5 V  
Max t of 10 ns at 5 V  
pd  
Inputs Are TTL-Voltage Compatible  
1
2
3
4
5
6
7
8
9
10  
20  
19  
18  
17  
16  
15  
14  
13  
12  
11  
OE  
1Q  
1D  
2D  
2Q  
3Q  
3D  
4D  
4Q  
V
CC  
8Q  
8D  
7D  
7Q  
6Q  
6D  
5D  
5Q  
LE  
description/ordering information  
These 8-bit latches feature 3-state outputs  
designed specifically for driving highly capacitive  
or relatively low-impedance loads. The devices  
are particularly suitable for implementing buffer  
registers, I/O ports, bidirectional bus drivers, and  
working registers.  
GND  
The eight latches are D-type transparent latches.  
When the latch-enable (LE) input is high, the Q  
outputs follow the data (D) inputs. When LE is  
taken low, the Q outputs are latched at the logic  
levels set up at the D inputs.  
SN54ACT373 . . . FK PACKAGE  
(TOP VIEW)  
A buffered output-enable (OE) input can be used  
to place the eight outputs in either a normal logic  
state (high or low logic levels) or the  
high-impedance state. In the high-impedance  
state, the outputs neither load nor drive the bus  
lines significantly. The high-impedance state and  
increased drive provide the capability to drive bus  
lines in bus-organized systems without need for  
interface or pullup components.  
3
2
1
20 19  
18  
8D  
7D  
7Q  
6Q  
6D  
2D  
2Q  
3Q  
3D  
4D  
4
5
6
7
8
17  
16  
15  
14  
9 10 11 12 13  
OE does not affect the internal operations of the latches. Old data can be retained or new data can be entered  
while the outputs are in the high-impedance state.  
To ensure the high-impedance state during power up or power down, OE should be tied to V through a pullup  
CC  
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.  
ORDERING INFORMATION  
ORDERABLE  
PART NUMBER  
TOP-SIDE  
MARKING  
†
PACKAGE  
T
A
PDIP – N  
Tube  
SN74ACT373N  
SN74ACT373N  
Tube  
SN74ACT373DW  
SN74ACT373DWR  
SN74ACT373NSR  
SN74ACT373DBR  
SN74ACT373PWR  
SNJ54ACT373J  
SOIC – DW  
ACT373  
Tape and reel  
Tape and reel  
Tape and reel  
Tape and reel  
Tube  
–40°C to 85°C  
SOP – NS  
SSOP – DB  
TSSOP – PW  
CDIP – J  
ACT373  
AD373  
AD373  
SNJ54ACT373J  
SNJ54ACT373W  
SNJ54ACT373FK  
–55°C to 125°C  
CFP – W  
Tube  
SNJ54ACT373W  
SNJ54ACT373FK  
LCCC – FK  
Tube  
†
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are  
available at www.ti.com/sc/package.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Copyright 2002, Texas Instruments Incorporated  
On products compliant to MIL-PRF-38535, all parameters are tested  
unless otherwise noted. On all other products, production  
processing does not necessarily include testing of all parameters.  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567...19

中文翻译

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SN74ACT373DWR 替代型号

型号 品牌 替代类型 描述 数据表
SN74ACT373DWG4 TI

完全替代

 OCTAL D-TYPE TRANSPARENT LATCHES WITH 3-STATE OUTPUTS
SN74ACT373DW TI

完全替代

 OCTAL D-TYPE TRANSPARENT LATCHES WITH 3-STATE OUTPUTS
MC74ACT373DWG ONSEMI

类似代替

 Octal Transparent Latch with 3−State Outputs

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SN74ACT373NE4 TI

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SN74ACT373NSR TI

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 		OCTAL D-TYPE TRANSPARENT LATCHES WITH 3-STATE OUTPUTS
SN74ACT373NSRE4 TI

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SN74ACT373NSRG4 TI

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 		OCTAL D-TYPE TRANSPARENT LATCHES WITH 3-STATE OUTPUTS
SN74ACT373PW TI

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 		OCTAL D-TYPE TRANSPARENT LATCHES WITH 3-STATE OUTPUTS

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